DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 653

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

11.4.10 MTU2–MTU2S Synchronous Operation
MTU2–MTU2S Synchronous Counter Start: The counters in the MTU2 and MTU2S which
operate at different clock systems can be started synchronously by making the TCSYSTR settings
in the MTU2.
1. Example of MTU2–MTU2S Synchronous Counter Start Setting Procedure
Figure 11.83 shows an example of synchronous counter start setting procedure.
MTU2-MTU2S synchronous
Set the necessary operation
<Counter operation starts>
Figure 11.83 Example of Synchronous Counter Start Setting Procedure
Stop count operation
Set TCSYSTR
counter start
[3]
[1]
[2]
[1] Use TSTR registers in the MTU2 and MTU2S and halt the
[2] Specify necessary operation with appropriate registers such as
[3] In TCSYSTR in the MTU2, set the bits corresponding to the
Notes: 1. Even if a bit in TCSYSTR corresponding to an operating
counters used for synchronous start operation.
TCR and TMDR.
counters to be started synchronously to 1. The TSTRs are
automatically set appropriately and the counters start
synchronously.
2. To start channels 3 and 4 in reset-synchronized PWM
counter is cleared to 0, the counter will not stop. To stop
the counter, clear the corresponding bit in TSTR to 0
directly.
mode or complementary PWM mode, make appropriate
settings in TCYSTR according to the TSTR setting for
the respective mode. For details, refer to section 11.4.7,
Reset-Synchronized PWM Mode, and section 11.4.8,
Complementary PWM Mode.
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 3.00 May 17, 2007 Page 595 of 1582
REJ09B0181-0300