DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 473

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

10.4.5
Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states
is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master.
For details, see section 9, Bus State Controller (BSC).
DREQ Pin Sampling Timing: Figures 10.14 to 10.17 show the sample timing of the DREQ input
in each bus mode, respectively.
Determination of DMAC activation by DREQ takes 3 × Bcyc (Bcyc is the external clock (Bφ =
CK) cycle). Timing of the DACK output for the first DREQ acceptance differs depending on the
internal bus state, the AM bit setting in CHCR, and the configuration of the BSC regarding the
transfer source/destination areas, but the fastest case is 6 × Bcyc.
Figure 10.14 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
Number of Bus Cycle States and DREQ Pin Sampling Timing
CK
Bus cycle
DREQ
(Rising edge)
DACK
(Active-high)
1st acceptance
CPU
Non-sensitive period
CPU
Section 10 Direct Memory Access Controller (DMAC)
DMAC
Acceptance started
Rev. 3.00 May 17, 2007 Page 415 of 1582
2nd acceptance
CPU
REJ09B0181-0300