DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 226

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 7 User Break Controller (UBC)
7.5
1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the
2. UBC cannot monitor access to the L bus and I bus in the same channel.
3. Note on specification of sequential break:
4. When a user break and another exception occur at the same instruction, which has higher
5. Note the following exception for the above note.
6. Note the following when a user break occurs in a delay slot.
Rev. 3.00 May 17, 2007 Page 168 of 1582
REJ09B0181-0300
period from executing an instruction to rewrite the UBC register till the new value is actually
rewritten, the desired user break may not occur. In order to know the timing when the UBC
register is changed, read from the last written register. Instructions after then are valid for the
newly written register value.
A condition match occurs when a B-channel match occurs in a bus cycle after an A-channel
match occurs in another bus cycle in sequential break setting. Therefore, no user break occurs
even if a bus cycle, in which an A-channel match and a channel B match occur simultaneously,
is set.
priority is determined according to the priority levels defined in table 5.1 in section 5,
Exception Handling. If an exception with higher priority occurs, the user break is not
generated.
 Pre-execution break has the highest priority.
 When a post-execution break or data access break occurs simultaneously with a re-
 When a post-execution break or data access break occurs simultaneously with a
If a post-execution break or data access break is satisfied by an instruction that generates a
CPU address error by data access, the CPU address error is given priority to the user break
interrupt. Note that the UBC condition match flag is set in this case.
If a pre-execution break is set at the delay slot instruction of the RTE instruction, the user
break does not occur until the branch destination of the RTE instruction.
execution-type exception (including pre-execution break) that has higher priority, the re-
execution-type exception is accepted, and the condition match flag is not set (see the
exception in the following note). The user break will occur and the condition match flag
will be set only after the exception source of the re-execution-type exception has been
cleared by the exception handling routine and re-execution of the same instruction has
ended.
completion-type exception (TRAPA) that has higher priority, though a user break does not
occur, the condition match flag is set.
Usage Notes