DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 1272

IC SUPERH MCU FLASH 112LQFP

DF70844AD80FPV

Manufacturer Part Number
DF70844AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet

Specifications of DF70844AD80FPV

Core Size
32-Bit
Program Memory Size
256KB (256K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
16KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF70844AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
DF70844AD80FPV
Quantity:
5 000
Section 22 I/O Ports
• PFDRL (SH7086)
Initial value:
Table 22.12 Port F Data Register L (PFDRL) Read/Write Operations
• PFDRL Bits 15 to 0
Rev. 3.00 May 17, 2007 Page 1214 of 1582
REJ09B0181-0300
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Pin Function
General input
ANn input (analog input)
R/W:
Bit:
PF15
DR
15
R
*
Bit Name
PF15DR
PF14DR
PF13DR
PF12DR
PF11DR
PF10DR
PF9DR
PF8DR
PF7DR
PF6DR
PF5DR
PF4DR
PF3DR
PF2DR
PF1DR
PF0DR
PF14
DR
14
R
*
PF13
DR
13
R
*
Initial
Value
Pin state R
Pin state R
Pin state R
Pin state R
Pin state R
Pin state R
Pin state R
Pin state R
Pin state R
Pin state R
Pin state R
Pin state R
Pin state R
Pin state R
Pin state R
Pin state R
PF12
DR
12
R
*
PF11
11
DR
R
*
R/W
Read
Pin state
1
PF10
DR
10
R
*
Description
See table 22.12.
PF9
DR
R
9
*
PF8
DR
R
8
*
PF7
DR
Write
Ignored (no effect on pin state)
Ignored (no effect on pin state)
R
7
*
PF6
DR
R
6
*
PF5
DR
R
5
*
PF4
DR
R
4
*
PF3
DR
R
3
*
PF2
DR
R
2
*
PF1
DR
R
1
*
PF0
DR
R
0
*

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