DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 751

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

13.3.4
OCSR2 is a 16-bit readable/writable register that controls the enable/disable of both output level
comparison and interrupts, and indicates status.
Initial value:
Bit
15
14 to 10 
9
8
Notes:
R/W:
Bit:
1.
2.
R/(W)*
OSF2
Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Can be modified only once after a power-on reset.
Output Level Control/Status Register 2 (OCSR2)
Bit Name
OSF2
OCE2
OIE2
15
0
1
14
R
0
-
13
Initial
value
0
All 0
0
0
R
0
-
12
R
0
-
R/W
R/(W)*
R
R/W*
R/W
11
R
0
-
2
10
R
0
-
1
Description
Output Short Flag 2
This flag indicates that any one of the three pairs of
MTU2S 2-phase outputs to be compared has
simultaneously become an active level.
[Clearing condition]
•
[Setting condition]
•
Reserved
These bits are always read as 0. The write value should
always be 0.
Output Short High-Impedance Enable 2
This bit specifies whether to place the pins in high-
impedance state when the OSF2 bit in OCSR2 is set to 1.
0: Does not place the pins in high-impedance state
1: Places the pins in high-impedance state
Output Short Interrupt Enable 2
This bit enables or disables interrupt requests when the
OSF2 bit in OCSR2 is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
R/W*
OCE2
9
0
By writing 0 to OSF2 after reading OSF2 = 1
When any one of the three pairs of 2-phase outputs
has simultaneously become an active level
2
R/W
OIE2
8
0
R
7
0
-
Rev. 3.00 May 17, 2007 Page 693 of 1582
R
6
0
-
Section 13 Port Output Enable (POE)
R
5
0
-
R
4
0
-
R
3
0
-
REJ09B0181-0300
R
2
0
-
R
1
0
-
R
0
0
-