DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 457

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

10.4.2
DMA transfer requests are basically generated in either the data transfer source or destination, but
they can also be generated by external devices or on-chip peripheral modules that are neither the
source nor the destination. Transfers can be requested in three modes: auto request, external
request, and on-chip peripheral module request. The request mode is selected in the RS3 to RS0
bits in CHCR0 to CHCR3.
(1)
When there is no transfer request signal from an external source, as in a memory-to-memory
transfer or a transfer between memory and an on-chip peripheral module unable to request a
transfer, auto-request mode allows the DMAC to automatically generate a transfer request signal
internally. When the DE bits in CHCR0 to CHCR3 and the DME bit in DMAOR are set to 1, the
transfer begins so long as the AE and NMIF bits in DMAOR and the TE bits in CHCR0 to
CHCR3 are all 0.
(2)
In this mode, a transfer is performed at the request signals (DREQ0 to DREQ3) of an external
device. Choose one of the modes shown in table 10.3 according to the application system. When
this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF =
0), a transfer is performed upon a request at the DREQ input.
Table 10.3 Selecting External Request Modes with RS Bits
Choose to detect DREQ by either the edge or level of the signal input with the DL bit and DS bit
in CHCR_0 to CHCR_3 as shown in table 10.4. The source of the transfer request does not have
to be the data transfer source or destination.
RS3
0
Auto-Request Mode
External Request Mode
RS2
0
DMA Transfer Requests
RS1
0
1
RS0
0
0
1
Address Mode
Dual address
mode
Single address
mode
Section 10 Direct Memory Access Controller (DMAC)
Source
Any
External memory,
memory-mapped
external device
External device with
DACK
Rev. 3.00 May 17, 2007 Page 399 of 1582
Destination
Any
External device with
DACK
External memory,
memory-mapped
external device
REJ09B0181-0300