DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 429

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

• When activation request is generated in the order of DMAC and DTC during external space access from CPU
• When activation request is generated in the order of DTC and DMAC during external space access from CPU
• When activation request is generated for DTC and DMAC at the same time during external space access from CPU
[Reference] When activation request is generated in the order of DMAC and DTC during access to an on-chip peripheral module by CPU
Figure 9.49 Bus Arbitration when DTC and DMAC Compete during External Space Access
Internal bus
DTC activation request
DMAC activation request
Internal bus
DTC activation request
DMAC activation request
Internal bus
DTC activation request
DMAC activation request
Internal bus
DTC activation request
DMAC activation request
Access to on-chip peripheral module from CPU
External space access from CPU
External space access from CPU
External space access from CPU
Transfer is started for the request that is generated first
Transfer is started for the request that is generated first
Transfer is started in accordance with the bus priority (DTC>DMAC)
Transfer is started in accordance with the bus priority (DTC>DMAC)
Priority determination
Priority determination
from CPU
DMAC
DTC
DTC
DTC
Rev. 3.00 May 17, 2007 Page 371 of 1582
DMAC
DMAC
DMAC
DTC
Section 9 Bus State Controller (BSC)
REJ09B0181-0300