DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 428

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
9.5.13
This LSI owns the bus mastership in normal state and releases the bus only when receiving a bus
request from an external device. This LSI has three bus masters: CPU, DMAC, and DTC. The bus
mastership is given to these bus masters in accordance with the following priority.
Request for bus mastership by external device (BREQ) > CPU > DTC > DMAC > CPU.
However, when DTC or DMAC is requesting the bus mastership, the CPU does not obtain the bus
mastership continuously.
The following cases should be noted regarding the external space access request from the CPU.
1. When the CSSTP2 bit is 1 in the bus function extending register (BSCHER), the external
2. When an activation request is generated in the order of DMAC and DTC while an external
Rev. 3.00 May 17, 2007 Page 370 of 1582
REJ09B0181-0300
space access request from the CPU has lower priority than the burst transfer request from the
DMAC and DTC transfer request with DTLOCK = 0 in the bus function extending register
(BSCHER).
space is being accessed by the CPU, DMA transfer is executed first and then DTC transfer.
Figure 9.49 shows the bus arbitration when the DTC and DMAC compete while an external
space is accessed by the CPU.
Bus Arbitration