DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 302

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
9.4.2
CSnBCR is a 32-bit readable/writable register that specifies the type of memory connected to the
respective space, the data bus width of the space, and the number of wait cycles between access
cycles.
Do not access external memory other than area 0 until the register initialization is complete.
Initial value:
Initial value:
Rev. 3.00 May 17, 2007 Page 244 of 1582
REJ09B0181-0300
Bit
0
Bit
31, 30
Note:
R/W:
R/W:
Bit:
Bit:
*
When the on-chip ROM is disabled, CS0BCR samples the value input through the MD0 and MD1 external pins that
specify the bus width when a power-on reset is performed.
CSn Space Bus Control Register (CSnBCR) (n = 0 to 8)
31
15
R
R
Bit Name
HIZCNT
0
0
Bit Name

-
-
R/W
30
14
R
0
0
-
TYPE[2:0]
R/W
R/W
29
13
IWW[1:0]
1
0
Initial
Value
0
Initial
Value
All 0
R/W
R/W
28
12
1
0
27
11
R
R
0
0
-
-
R/W
R
R/W
R/W
R/W
R/W
IWRWD[1:0]
26
10
1*
1
BSZ[1:0]
Description
High-Z Control
Specifies the state in software standby mode and when
bus mastership is released for CKE, RASU, RASL,
CASU, and CASL.
0: High impedance in software standby mode and when
1: Driven in software standby mode and when bus
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W
R/W
25
1*
1
9
bus mastership is released for CKE, RASU, RASL,
CASU, and CASL.
mastership is released for CKE, RASU, RASL,
CASU, and CASL.
24
R
R
0
8
0
-
-
R/W
IWRWS[1:0]
23
R
1
7
0
-
R/W
22
R
1
6
0
-
21
R
R
0
5
0
-
-
R/W
IWRRD[1:0]
20
R
1
4
0
-
R/W
19
R
1
3
0
-
18
R
R
0
2
0
-
-
R/W
IWRRS[1:0]
17
R
1
1
0
-
R/W
16
R
1
0
0
-