DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 193

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

The user break controller (UBC) provides functions that simplify program debugging. These
functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug
programs without using an in-circuit emulator. Break conditions that can be set in the UBC are
instruction fetch or data read/write access, data size, data contents, address value, and stop timing
in the case of instruction fetch.
For the mask ROM version, only the L-bus instruction-fetch address break (2 channels) is
available.
7.1
The UBC has the following features:
1. The following break comparison conditions can be set.
• Address
• Data
• Bus cycle
• Read/write
• Operand size
2. A user-designed user-break interrupt exception processing routine can be run.
3. In an instruction fetch cycle, it can be selected that a user break is set before or after an
4. Maximum repeat times for the break condition (only for channel B): 2
5. Four pairs of branch source/destination buffers (eight pairs for F-ZTAT version supporting full
Number of break channels: two channels (channels A and B)
User break can be requested as either the independent or sequential condition on channels A
and B (sequential break setting: channel A and then channel B match with break conditions,
but not in the same bus cycle).
Comparison bits are maskable in 1-bit units.
One of the two address buses (L-bus address (LAB) and I-bus address (IAB)) can be selected.
32-bit maskable.
One of the two data buses (L-bus data (LDB) and I-bus data (IDB)) can be selected.
Instruction fetch or data access
Byte, word, and longword
instruction is executed.
functions of E10A).
Features
Section 7 User Break Controller (UBC)
Rev. 3.00 May 17, 2007 Page 135 of 1582
Section 7 User Break Controller (UBC)
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REJ09B0181-0300