DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 263

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 8.10 Number of Cycles Required for Each Execution State
Notes: 1. Values for on-chip RAM. Number of cycles varies depending on the ratio of Iφ:Bφ.
Object to be Accessed
Bus width
Access cycles
Execu-
tion
status
Vector read S
Transfer information read S
Transfer information write S
Byte data read S
Word data read S
Longword data read S
Byte data write S
Word data write S
Longword data write S
Internal operation S
2. Values for on-chip ROM. Number of cycles varies depending on the ratio of Iφ:Bφ.and
3. The values in the table are those for the fastest case. Depending on the state of the
4. This applies to the I
5. Values are different depending on the BSC register setting. The values in the table are
6. Values are different depending on the bus state.
are the same as on-chip RAM. Only vector read is possible.
internal bus, replace 1Bφ by 1Pφ in a slow case.
the sample for the case with no wait cycles and the WM bit in CSnWCR = 1.
The number of cycles increases when many external wait cycles are inserted in the
case where writing is frequently executed, such as block transfer, and when the
external bus is in use because the write buffer cannot be used efficiently in such cases.
For details on the write buffer, see section 9.5.14 (2), Access in View of LSI Internal
Bus Master.
Iφ:Bφ = 1:1
Iφ:Bφ = 1:1/2
Iφ:Bφ = 1:1/3
Iφ:Bφ = 1:1/4 or less
I
L
M
L
M
N
L
M
2
C2.
J
k
On-Chip
RAM*
32 bits
1Bφ to 3Bφ*
1Bφ to 3Bφ*
1Bφ to 3Bφ*
1Bφ to 3Bφ*
1Bφ to 3Bφ*
1Bφ to 3Bφ*
1Bφ to 3Bφ*
1Bφ to 3Bφ*
1Bφ to 3Bφ*
1Bφ to 3Bφ*
1
/ROM*
Read
3Bφ
2Bφ
2Bφ
1Bφ
1
1
1
1
1
1
1
1
1
1
*
*
2
2
2
8 bits*
2Pφ



1Bφ + 2Pφ*


1Bφ + 2Pφ*


On-Chip I/O Registers
4
3
3
Rev. 3.00 May 17, 2007 Page 205 of 1582
Write
3Bφ
1Bφ
1Bφ
1Bφ
Section 8 Data Transfer Controller (DTC)
16 bits
2Pφ



1Bφ + 2Pφ*
1Bφ + 2Pφ*
1Bφ + 4Pφ*
1Bφ + 2Pφ*
1Bφ + 2Pφ*
1Bφ + 4Pφ*
1
3
3
3
3
3
3
8 bits
2Bφ
9Bφ
9Bφ
2Bφ*
3Bφ
5Bφ
9Bφ
2Bφ*
2Bφ*
2Bφ*
External Devices*
6
6
6
6
REJ09B0181-0300
16 bits 32 bits
2Bφ
5Bφ
5Bφ
2Bφ*
3Bφ
3Bφ
5Bφ
2Bφ*
2Bφ*
2Bφ*
6
6
6
6
2Bφ
3Bφ
3Bφ
2Bφ*
3Bφ
3Bφ
3Bφ
2Bφ*
2Bφ*
2Bφ*
5
6
6
6
6