DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 564

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.27 Timer Cycle Buffer Register (TCBR)
TCBR is a 16-bit register used only in complementary PWM mode. It functions as a buffer
register for the TCDR register. The TCBR register values are transferred to the TCDR register
with the transfer timing set in the TMDR register.
The initial value of TCBR is H'FFFF.
Initial value:
11.3.28 Timer Interrupt Skipping Set Register (TITCR)
TITCR is an 8-bit readable/writable register that enables or disables interrupt skipping and
specifies the interrupt skipping count. The MTU2 has one TITCR.
Rev. 3.00 May 17, 2007 Page 506 of 1582
REJ09B0181-0300
Bit
7
6 to 4
3
Note:
R/W:
Bit:
Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units.
Bit Name
T3AEN
3ACOR[2:0] 000
T4VEN
R/W
15
1
R/W
14
1
R/W
13
Initial value:
1
Initial
value
0
0
R/W
R/W:
12
1
Bit:
T3AEN
R/W
R/W
11
1
7
0
R/W
R/W
R/W
R/W
R/W
R/W
10
1
6
0
3ACOR[2:0]
Description
T3AEN
Enables or disables TGIA_3 interrupt skipping.
0: TGIA_3 interrupt skipping disabled
1: TGIA_3 interrupt skipping enabled
These bits specify the TGIA_3 interrupt skipping count
within the range from 0 to 7.*
For details, see table 11.40.
T4VEN
Enables or disables TCIV_4 interrupt skipping.
0: TCIV_4 interrupt skipping disabled
1: TCIV_4 interrupt skipping enabled
R/W
R/W
9
1
5
0
R/W
R/W
8
1
4
0
T4VEN
R/W
R/W
7
1
3
0
R/W
R/W
6
1
2
0
4VCOR[2:0]
R/W
R/W
5
1
1
0
R/W
R/W
4
1
0
0
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1