DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 1302

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 23 Flash Memory
(3.3) Flash pass/fail result parameter (FPFR: general register R0 of CPU)
Initial value:
Initial value:
Rev. 3.00 May 17, 2007 Page 1244 of 1582
REJ09B0181-0300
Bit
31 to 7 
6
This parameter indicates the return value of the program processing result.
R/W:
R/W:
Bit:
Bit:
Bit Name
MD
R/W
R/W
31
15
-
-
-
-
R/W
R/W
30
14
-
-
-
-
R/W
R/W
Initial
Value
Undefined R/W
Undefined R/W
29
13
-
-
-
-
R/W
R/W
28
12
-
-
-
-
R/W
R/W
27
11
-
-
-
-
R/W
R/W
R/W
26
10
-
-
-
-
Description
Unused
Return 0.
Programming Mode Related Setting Error Detect
Returns the check result of whether the signal input to
the FWE pin is high and whether the error protection
state is not entered.
When a low-level signal is input to the FWE pin or the
error protection state is entered, 1 is written to this bit.
The input level to the FWE pin and the error protection
state can be confirmed with the FWE bit (bit 7) and the
FLER bit (bit 4) in FCCS, respectively. For conditions to
enter the error protection state, see section 23.6.3,
Error Protection.
0: FWE and FLER settings are normal (FWE = 1, FLER
1: FWE = 0 or FLER = 1, and programming cannot be
R/W
R/W
25
9
-
-
-
-
= 0)
performed
R/W
R/W
24
8
-
-
-
-
R/W
R/W
23
7
-
-
-
-
R/W
R/W
MD
22
6
-
-
-
R/W
R/W
21
EE
5
-
-
-
R/W
R/W
20
FK
4
-
-
-
R/W
R/W
19
3
-
-
-
-
R/W
R/W
WD
18
2
-
-
-
R/W
R/W
WA
17
1
-
-
-
R/W
R/W
16
SF
0
-
-
-