DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 205

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

7.3.9
BDMRB is a 32-bit readable/writable register. BDMRB specifies bits masked in the break data
specified by BDRB.
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
Initial value:
Initial value:
Bit
31 to 0 BDMB31 to
R/W:
R/W:
Bit:
Bit:
2. When the byte size is selected as a break condition, the same byte data must be set in
BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16
BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9
Bit Name
BDMB 0
R/W
R/W
Break Data Mask Register B (BDMRB) (Only in F-ZTAT Version)
31
15
0
0
bits 15 to 8 and 7 to 0 in BDMRB as the break mask data in BDRB.
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
All 0
R/W
R/W
28
12
0
0
R/W
R/W
27
11
R/W
R/W
0
0
R/W
R/W
26
10
0
0
Description
Break Data Mask B
Specifies bits masked in the break data of channel B
specified by BDRB (BDB31 to BDB0).
0: Break data BDBn of channel B is included in the
1: Break data BDBn of channel B is masked and is not
Note: n = 31 to 0
R/W
R/W
25
0
9
0
break condition
included in the break condition
BDMB8
R/W
R/W
24
0
8
0
BDMB7
R/W
R/W
23
0
7
0
BDMB6
R/W
R/W
Rev. 3.00 May 17, 2007 Page 147 of 1582
22
0
6
0
Section 7 User Break Controller (UBC)
BDMB5
R/W
R/W
21
0
5
0
BDMB4
R/W
R/W
20
0
4
0
BDMB3
R/W
R/W
19
0
3
0
REJ09B0181-0300
BDMB2
R/W
R/W
18
0
2
0
BDMB1
R/W
R/W
17
0
1
0
BDMB0
R/W
R/W
16
0
0
0