DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 797

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Note: *
Bit
2
1
0
Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Bit Name
TEND
MPB
MPBT
Initial
value
1
0
0
R/W
R
R
R/W
Description
Transmit End
Indicates that no valid data was in SCTDR during
transmission of the last bit of the transmit character
and transmission has ended.
The TEND flag is read-only and cannot be modified.
0: Indicates that transmission is in progress
[Clearing condition]
•
1: Indicates that transmission has ended
[Setting conditions]
•
•
•
Note: The TEND flag value becomes undefined if
Multiprocessor Bit
Stores the multiprocessor bit found in the receive
data. When the RE bit in SCSCR is cleared to 0, its
previous state is retained.
Multiprocessor Bit Transfer
Specifies the multiprocessor bit value to be added to
the transmit frame.
When 0 is written to TDRE after reading TDRE = 1
By a power-on reset or in standby mode
When the TE bit in SCSCR is 0
When TDRE = 1 during transmission of the last bit
of a 1-byte serial transmit character
data is written to SCTDR by activating the
DMAC or DTC by a TXI interrupt. In this case,
do not use the TEND flag as the transmit end
flag.
Section 15 Serial Communication Interface (SCI)
Rev. 3.00 May 17, 2007 Page 739 of 1582
REJ09B0181-0300