DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 930

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 17 Synchronous Serial Communication Unit (SSU)
17.3.6
SSCR2 is a register that selects the assert timing of the SCS pin, data output timing of the SSO
pin, and set timing of the TEND bit.
Rev. 3.00 May 17, 2007 Page 872 of 1582
REJ09B0181-0300
Bit
7 to 5
4
3
2
1, 0
Bit Name

TENDSTS 0
SCSATS
SSODTS

SS Control Register 2 (SSCR2)
Initial
Value
All 0
0
0
All 0
Initial value:
R/W:
Bit:
R/W
R
R/W
R/W
R/W
R
R
7
0
-
R
6
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Selects the timing of setting the TEND bit (valid in SSU
and master mode).
0: Sets the TEND bit when the last bit is being
1: Sets the TEND bit after the last bit is transmitted
Selects the assertion timing of the SCS pin (valid in
SSU and master mode).
0: Min. values of t
1: Min. values of t
Selects the data output timing of the SSO pin (valid in
SSU and master mode)
0: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
1: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
Reserved
These bits are always read as 0. The write value should
always be 0.
R
5
0
-
transmitted
= 1, TE = 1, and RE = 0, the SSO pin outputs data
= 1, TE = 1, and RE = 0, the SSO pin outputs data
while the SCS pin is driven low
TENDSTS
R/W
4
0
SCSATS SSODTS
R/W
3
0
LEAD
LEAD
R/W
2
0
and t
and t
R
1
0
-
LAG
LAG
are 1/2 × t
are 3/2 × t
R
0
0
-
SUcyc
SUcyc