DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 1600

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Rev. 3.00 May 17, 2007 Page 1542 of 1582
REJ09B0181-0300
Item
4.5 Changing Frequency
Table 5.5 Reset Status
Section 7 User Break Controller
(UBC)
7.1 Features
Table 7.2 Register Configuration
Page Revision (See Manual for Details)
81
91
135
135
138
fetch address break (2 channels) is available.
Amended
3. …..When using the MTU2S clock and MTU2 clock,
4. After an instruction to rewrite FRQCR has been
Note:
Amended
Added
….Break conditions that can be set in the UBC are
instruction fetch or data read/write access, data size,
data contents, address value, and stop timing in the
case of instruction fetch.
For the mask ROM version, only the L-bus instruction-
Amended
5.
Note added.
Note: * Only in F-ZTAT version
Type
Power-on reset
Manual reset
specify the frequencies to satisfy the following
condition: internal clock (Iφ) ≥ MTU2S clock (MIφ) ≥
MTU2 clock (MPφ) ≥ peripheral clock (Pφ) and bus
clock (Bφ) ≥ MTU2 clock (MPφ).
Code to rewrite values of FRQCR should be
executed in the on-chip ROM or on-chip RAM.
issued, the actual clock frequencies will change after
(1 to 24n) cyc + 11Bφ + 7Pφ.
n: Division ratio specified by the BFC bit in FRQCR
(1, 1/2, 1/3, 1/4, or 1/8)
cyc: Clock obtained by dividing EXTAL by 8 with the
PLL.
Four pairs of branch source/destination buffers
(eight pairs for F-ZTAT version supporting full
functions of E10A).
(1 to 24n) depends on the internal state.
Internal State
POE, PFC, I/O Port
Initialized
Initialized
Not initialized