HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 16

• Manufacturer Part Number: HD64F3048VTF8
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048VTF8

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F3048VX8

6.3
6.4
Section 7
7.1
7.2
7.3
7.4
7.5
Section 8
8.1
Rev. 7.00 Sep 21, 2005 page xiv of xxiv
Operation .......................................................................................................................... 133
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
Usage Notes ...................................................................................................................... 156
6.4.1
6.4.2
6.4.3
6.4.4
Overview........................................................................................................................... 159
7.1.1
7.1.2
7.1.3
7.1.4
Register Descriptions ........................................................................................................ 162
7.2.1
7.2.2
7.2.3
7.2.4
Operation .......................................................................................................................... 168
7.3.1
7.3.2
7.3.3
7.3.4
Interrupt Source ................................................................................................................ 195
Usage Notes ...................................................................................................................... 195
Overview........................................................................................................................... 197
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
Area Division....................................................................................................... 133
Chip Select Signals .............................................................................................. 134
Data Bus............................................................................................................... 136
Bus Control Signal Timing .................................................................................. 137
Wait Modes.......................................................................................................... 145
Interconnections with Memory (Example) .......................................................... 151
Bus Arbiter Operation.......................................................................................... 153
Connection to Dynamic RAM and Pseudo-Static RAM...................................... 156
Register Write Timing ......................................................................................... 156
BREQ Input Timing............................................................................................. 158
Transition To Software Standby Mode ................................................................ 158
Refresh Controller
Features................................................................................................................ 159
Block Diagram..................................................................................................... 160
Input/Output Pins ................................................................................................. 161
Register Configuration......................................................................................... 161
Refresh Control Register (RFSHCR)................................................................... 162
Refresh Timer Control/Status Register (RTMCSR) ............................................ 165
Refresh Timer Counter (RTCNT)........................................................................ 166
Refresh Time Constant Register (RTCOR) ......................................................... 167
Overview.............................................................................................................. 168
DRAM Refresh Control....................................................................................... 170
Pseudo-Static RAM Refresh Control ................................................................... 185
Interval Timer ...................................................................................................... 189
DMA Controller
Features................................................................................................................ 197
Block Diagram..................................................................................................... 198
Functional Overview............................................................................................ 199
Input/Output Pins ................................................................................................. 201
Register Configuration......................................................................................... 201
............................................................................................. 197
.......................................................................................... 159