HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 558

• Manufacturer Part Number: HD64F3048VTF8
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048VTF8

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F3048VX8

Section 14 Smart Card Interface
From this equation, if F = 0 and D = 0.5 the receive margin is as follows.
Retransmission: Retransmission is described below for the separate cases of transmit mode and
receive mode.
(1) The SCI checks the received parity bit. If it detects an error, it automatically sets the PER flag
(2) The RDRF bit in SSR is not set to 1 for the error frame.
(3) If an error is not detected when the parity bit is checked, the PER flag is not set in SSR.
(4) If an error is not detected when the parity bit is checked, receiving operations are assumed to
(5) When a normal frame is received, at the error signal transmit timing, the data pin is held in the
Rev. 7.00 Sep 21, 2005 page 532 of 878
REJ09B0259-0700
Retransmission when SCI is in Receive Mode (see figure 14.11)
to 1. If the RIE bit in SCR is set to the enable state, an ERI interrupt is requested. The PER flag
should be cleared to 0 in SSR before the next parity bit sampling timing.
have ended normally, and the RDRF bit is automatically set to 1 in SSR. If the RIE bit in SCR
is set to the enable state, an RXI interrupt is requested. If RXI is enabled as a DMA transfer
activation source, the RDR contents can be read automatically. When the DMAC reads the
RDR data, it automatically clears RDRF to 0.
high-impedance state.
RDRF
PER
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
D = 0.5, F = 0
M = {0.5 – 1/(2
= 49.866%
Frame n
Figure 14.11 Retransmission in SCI Receive Mode
372)}
100%
DE
(2)
(1)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Retransmitted frame
(DE)
(4)
(3)
Ds
D0 D1 D2 D3 D4
Frame n + 1