HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 196

• Manufacturer Part Number: HD64F3048VTF8
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048VTF8

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F3048VX8

Section 7 Refresh Controller
7.3.2
Refresh Request Interval and Refresh Cycle Execution: The refresh request interval is
determined by the settings of RTCOR and bits CKS2 to CKS0 in RTMCSR. Figure 7.2 illustrates
the refresh request interval.
Refresh requests are generated at regular intervals as shown in figure 7.2, but the refresh cycle is
not actually executed until the refresh controller gets the bus right.
Table 7.4 summarizes the relationship among area 3 settings, DRAM read/write cycles, and
refresh cycles.
Table 7.4
Area 3 Settings
2-state-access area
(AST3 = 0)
3-state-access area
(AST3 = 1)
To insert refresh cycles, set the RCYCE bit to 1 in RFSHCR. Figure 7.3 shows the state transitions
for execution of refresh cycles.
When the first refresh request occurs after exit from the reset state or standby mode, the refresh
controller does not execute a refresh cycle, but goes into the refresh request pending state. Note
this point when using a DRAM that requires a refresh cycle for initialization.
Rev. 7.00 Sep 21, 2005 page 170 of 878
REJ09B0259-0700
RTCOR
H'00
Refresh request
DRAM Refresh Control
Area 3 Settings, DRAM Access Cycles, and Refresh Cycles
Figure 7.2 Refresh Request Interval (RCYCE = 1)
Read/Write Cycle by CPU
or DMAC
3 states
Wait states cannot be inserted
3 states
Wait states can be inserted
RTCNT
Refresh Cycle
3 states
Wait states cannot be inserted
3 states
Wait states can be inserted