HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 362

• Manufacturer Part Number: HD64F3048VTF8
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048VTF8

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F3048VX8

Section 10 16-Bit Integrated Timer Unit (ITU)
Bit 3—Master Enable TIOCB3 (EB3): Enables or disables ITU output at pin TIOCB
Bit 2—Master Enable TIOCB4 (EB4): Enables or disables ITU output at pin TIOCB
Bit 1—Master Enable TIOCA4 (EA4): Enables or disables ITU output at pin TIOCA
Bit 0—Master Enable TIOCA3 (EA3): Enables or disables ITU output at pin TIOCA
Rev. 7.00 Sep 21, 2005 page 336 of 878
REJ09B0259-0700
Bit 3: EB3
0
1
Bit 2: EB4
0
1
Bit 1: EA4
0
1
Bit 0: EA3
0
1
Description
TIOCB
operates as a generic input/output pin).
If XTGD = 0, EB3 is cleared to 0 when input capture A occurs in channel 1.
TIOCB
Description
TIOCB
operates as a generic input/output pin).
If XTGD = 0, EB4 is cleared to 0 when input capture A occurs in channel 1.
TIOCB
Description
TIOCA
(TIOCA
If XTGD = 0, EA4 is cleared to 0 when input capture A occurs in channel 1.
TIOCA
Description
TIOCA
(TIOCA
If XTGD = 0, EA3 is cleared to 0 when input capture A occurs in channel 1.
TIOCA
3
3
4
4
4
4
3
3
4
3
output is disabled regardless of TIOR3 and TFCR settings (TIOCB
is enabled for output according to TIOR3 and TFCR settings
output is disabled regardless of TIOR4 and TFCR settings (TIOCB
is enabled for output according to TIOR4 and TFCR settings
output is disabled regardless of TIOR4, TMDR, and TFCR settings
is enabled for output according to TIOR4, TMDR, and TFCR settings
output is disabled regardless of TIOR3, TMDR, and TFCR settings
is enabled for output according to TIOR3, TMDR, and TFCR settings
operates as a generic input/output pin).
operates as a generic input/output pin).
(Initial value)
(Initial value)
(Initial value)
(Initial value)
3
4
4
3
.
.
.
.
3
4