HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 684

• Manufacturer Part Number: HD64F3048VTF8
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048VTF8

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F3048VX8

Section 20 Clock Pulse Generator
External Clock: The external clock frequency should be equal to the system clock frequency ( )
when not divided by the on-chip frequency divider. Table 20.3, figures 20.6 and 20.7 indicate the
clock timing.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the
on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external
devices after the external clock settling time (t
must remain reset with the reset signal low during t
Table 20.3 Clock Timing
Item
External clock
input low pulse
width
External clock
input high pulse
width
External clock
rise time
External clock
fall time
Clock low pulse
width
Clock high pulse
width
External clock
output settling
delay time
Note: * t
Rev. 7.00 Sep 21, 2005 page 658 of 878
REJ09B0259-0700
DEXT
includes 10 t
Symbol
t
t
t
t
t
t
t
EXL
EXH
EXr
EXf
CL
CH
DEXT
*
cyc
of RES (t
Min
40
40
—
—
0.4
80
0.4
80
500
2.7 V to 5.5 V
V
RESW
CC
Max
—
—
10
10
0.6
—
0.6
—
—
=
).
DEXT
) has passed after the clock input. The system
DEXT
Min
20
20
—
—
0.4
80
0.4
80
500
5.0 V ± 10%
, while the clock output is unstable.
V
CC
Max
—
—
5
5
0.6
—
0.6
—
—
=
Unit
ns
ns
ns
ns
t
ns
t
ns
µs
cyc
cyc
Test Conditions
Figure 20.6
Figure 20.7
< 5 MHz
< 5 MHz
5 MHz
5 MHz
Figure
22.7