HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 239

• Manufacturer Part Number: HD64F3048VTF8
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048VTF8

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F3048VX8

Bit 7—Data Transfer Enable (DTE): Together with the DTME bit in DTCRB, this bit enables
or disables data transfer on the channel. When the DTME and DTE bits are both set to 1, the
channel is enabled. If auto-request is specified, data transfer begins immediately. Otherwise, the
channel waits for transfers to be requested. When the specified number of transfers have been
completed, the DTE bit is automatically cleared to 0. When DTE is 0, the channel is disabled and
does not accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then
writing 1.
If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0.
Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer.
Bit 5—Source Address Increment/Decrement (SAID) and
Bit 4—Source Address Increment/Decrement Enable (SAIDE): These bits select whether the
source address register (MARA) is incremented, decremented, or held fixed during the data
transfer.
Bit 7: DTE
0
1
Bit 6: DTSZ
0
1
Bit 5: SAID
0
1
Bit 4: SAIDE
0
1
0
1
Description
Data transfer is disabled (DTE is cleared to 0 when the specified number of
transfers have been completed)
Data transfer is enabled
Description
Byte-size transfer
Word-size transfer
Description
MARA is held fixed
MARA is incremented after each data transfer
MARA is held fixed
MARA is decremented after each data transfer
If DTSZ = 0, MARA is incremented by 1 after each transfer
If DTSZ = 1, MARA is incremented by 2 after each transfer
If DTSZ = 0, MARA is decremented by 1 after each
transfer
If DTSZ = 1, MARA is decremented by 2 after each
transfer
Rev. 7.00 Sep 21, 2005 page 213 of 878
Section 8 DMA Controller
REJ09B0259-0700
(Initial value)
(Initial value)
(Initial value)