HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 557

• Manufacturer Part Number: HD64F3048VTF8
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048VTF8

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F3048VX8

14.4
When using the SCI as a smart card interface, note the following points.
Receive Data Sampling Timing in Smart Card Mode and Receive Margin: In smart card
mode the SCI operates on a base clock with 372 times the bit rate frequency. In receiving, the SCI
synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive
data is latched at the rising edge of the 186th base clock pulse. See figure 14.10.
The receive margin can therefore be expressed as follows.
Receive margin in smart card mode:
Internal
base clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
M =
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 372)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute deviation of clock frequency
Usage Notes
Figure 14.10 Receive Data Sampling Timing in Smart Card Mode
0.5 –
2N
1
0
186 clocks
– (L – 0.5) F –
185
372 clocks
Start
bit
371
D – 0.5
N
0
D0
(1 + F)
Rev. 7.00 Sep 21, 2005 page 531 of 878
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Section 14 Smart Card Interface
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REJ09B0259-0700
0
D1