HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 17

• Manufacturer Part Number: HD64F3048VTF8
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048VTF8

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F3048VX8

8.2
8.3
8.4
8.5
8.6
Section 9
9.1
9.2
Register Descriptions (Short Address Mode).................................................................... 203
8.2.1
8.2.2
8.2.3
8.2.4
Register Descriptions (Full Address Mode)...................................................................... 209
8.3.1
8.3.2
8.3.3
8.3.4
Operation........................................................................................................................... 218
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.4.9
8.4.10 External Bus Requests, Refresh Controller, and DMAC ..................................... 246
8.4.11 NMI Interrupts and DMAC.................................................................................. 247
8.4.12 Aborting a DMA Transfer.................................................................................... 248
8.4.13 Exiting Full Address Mode .................................................................................. 249
8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode.......................... 250
Interrupts ........................................................................................................................... 251
Usage Notes ...................................................................................................................... 252
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.6.7
8.6.8
Overview........................................................................................................................... 257
Port 1................................................................................................................................. 261
9.2.1
Memory Address Registers (MAR) ..................................................................... 203
I/O Address Registers (IOAR) ............................................................................. 204
Execute Transfer Count Registers (ETCR) .......................................................... 205
Data Transfer Control Registers (DTCR) ............................................................ 206
Memory Address Registers (MAR) ..................................................................... 209
I/O Address Registers (IOAR) ............................................................................. 209
Execute Transfer Count Registers (ETCR) .......................................................... 210
Data Transfer Control Registers (DTCR) ............................................................ 212
Overview.............................................................................................................. 218
I/O Mode.............................................................................................................. 220
Idle Mode............................................................................................................. 222
Repeat Mode ........................................................................................................ 225
Normal Mode ....................................................................................................... 229
Block Transfer Mode ........................................................................................... 232
DMAC Activation................................................................................................ 237
DMAC Bus Cycle ................................................................................................ 239
DMAC Multiple-Channel Operation ................................................................... 245
Note on Word Data Transfer................................................................................ 252
DMAC Self-Access.............................................................................................. 252
Longword Access to Memory Address Registers ................................................ 252
Note on Full Address Mode Setup ....................................................................... 252
Note on Activating DMAC by Internal Interrupts ............................................... 252
NMI Interrupts and Block Transfer Mode ........................................................... 254
Memory and I/O Address Register Values .......................................................... 254
Bus Cycle when Transfer is Aborted ................................................................... 255
Overview.............................................................................................................. 261
I/O Ports
............................................................................................................ 257
Rev. 7.00 Sep 21, 2005 page xv of xxiv