HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 506

• Manufacturer Part Number: HD64F3048VTF8
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048VTF8

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F3048VX8

Section 13 Serial Communication Interface
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected
by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. See table 13.9.
When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the
desired bit rate.
When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The
frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 13.3 so that
the rising edge of the clock occurs at the center of each transmit data bit.
Transmitting and Receiving Data
Rev. 7.00 Sep 21, 2005 page 480 of 878
REJ09B0259-0700
SCI Initialization (Asynchronous Mode)
Before transmitting or receiving, clear the TE and RE bits to 0 in SCR, then initialize the SCI
as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0
before following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and
initializes TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and
ORER flags and RDR, which retain their previous contents.
When an external clock is used, the clock should not be stopped during initialization or
subsequent operation. SCI operation becomes unreliable if the clock is stopped.
Figure 13.4 is a sample flowchart for initializing the SCI.
Figure 13.3 Phase Relationship between Output Clock and Serial Data
0
D0
D1
D2
D3
(Asynchronous Mode)
D4
1 frame
D5
D6
D7
0/1
1
1