HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 74

• Manufacturer Part Number: HD64F3048VTF8
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048VTF8

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F3048VX8

Section 2 CPU
Figure 2.9 shows examples of instruction formats.
2.6.5
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the
byte, then write the byte back. Care is required when these instructions are used to access registers
with write-only bits, or to access ports.
The BCLR instruction can be used to clear flags in the internal I/O registers. In an interrupt-
handling routine, for example, if it is known that the flag is set to 1, it is not necessary to read the
flag ahead of time.
Step
1
2
3
In the following example, a BCLR instruction is executed on the data direction register (DDR) of
port 4.
P4
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Operation field only
Operation field and register fields
Operation field, register fields, and effective address extension
Operation field, effective address extension, and condition field
and P4
Read
Bit manipulation
Write
Notes on Use of Bit Manipulation Instructions
op
6
are set as input pins, and are inputting low-level and high-level signals, respectively.
op
op
cc
Figure 2.9 Instruction Formats
EA (disp)
Description
Read data (byte unit) at the specified address
Modify the specified bit in the read data
Write the modified data (byte unit) to the specified address
op
rn
rn
EA (disp)
rm
rm
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B @(d:16, Rn), Rm
BRA d:8