HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 515

• Manufacturer Part Number: HD64F3048VTF8
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048VTF8

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F3048VX8

Transmitting and Receiving Data
Transmitting Multiprocessor Serial Data
Figure 13.10 shows a sample flowchart for transmitting multiprocessor serial data and
indicates the procedure to follow.
Clear DR bit to 0, set DDR bit to 1
Figure 13.10 Sample Flowchart for Transmitting Multiprocessor Serial Data
TDR and set MPBT bit in SSR
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit to 0 in SCR
Write transmit data in
Clear TDRE flag to 0
Output break signal?
All data transmitted?
Start transmitting
TDRE = 1?
TEND = 1?
Initialize
End
Yes
Yes
Yes
Yes
No
No
No
No
1
2
3
4
1.
2.
3.
4.
Section 13 Serial Communication Interface
SCI initialization: the transmit data
output function of the TxD pin is
selected automatically.
SCI status check and transmit data
write: read SSR, check that the TDRE
flag is 1, then write transmit
data in TDR. Also set the MPBT flag to
0 or 1 in SSR. Finally, clear the TDRE
flag to 0.
To continue transmitting serial data:
after checking that the TDRE flag is 1,
indicating that data can be
written, write data in TDR, then clear
the TDRE flag to 0. When the DMAC
is activated by a transmit-data-empty
interrupt request (TXI) to write data in
TDR, the TDRE flag is checked and
cleared automatically.
To output a break signal at the end of
serial transmission: set the DDR bit to
1 and clear the DR bit to 0 (DDR and
DR are I/O port registers), then clear
the TE bit to 0 in SCR.
Rev. 7.00 Sep 21, 2005 page 489 of 878
REJ09B0259-0700