HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 654

• Manufacturer Part Number: HD64F3048VTF8
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048VTF8

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F3048VX8

Section 19 Flash Memory (H8/3048F: Dual Power Supply (V
constant internal and external supervision, using the watchdog timer for example. If a transition to
error-protect mode occurs, the flash memory may contain incorrect data due to errors in
programming or erasing, or it may contain data that has been insufficiently programmed or erased
because of the suspension of these operations. Boot mode should be used to recover to a normal
state.
If the memory contains overerased memory cells, boot mode may not operate correctly. This is
because the H8/3048F’s built-in boot program is located in part of flash memory, and will not read
correctly if memory cells have been overerased.
19.5.9
NMI input is disabled when flash memory is being programmed or erased (when the P or E bit is
set in FLMCR). NMI input is also disabled while the boot program is executing in boot mode,
until the branch to the on-chip RAM area takes place *
NMI input is also disabled in the error-protect state while the P or E bit remains set in the flash
memory control register (FLMCR).
NMI requests should be disabled externally whenever V
Notes: 1. The disabled state lasts until the branch to the boot program area in on-chip RAM
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REJ09B0259-0700
NMI input during programming or erasing might cause a violation of the programming or
erasing algorithm. Normal operation could not be assured.
In the NMI exception-handling sequence during programming or erasing, the vector would not
be read correctly *
If NMI input occurred during boot program execution, the normal boot-mode sequence could
not be executed.
2. The vector may not be read correctly for the following two reasons.
NMI Input Masking
(addresses H'FFEF10 to H'FFF2FF) that takes place as soon as the transfer of the user
program is completed. After the branch to the RAM area, NMI input is enabled except
during programming or erasing. NMI interrupt requests must therefore be disabled
externally until the user program has completed initial programming (including the
vector table and the NMI interrupt-handling program).
• If flash memory is read while being programmed or erased (while the P or E bit is
• If the NMI entry in the vector table has not been programmed yet, NMI exception
set in FLMCR), correct read data will not be obtained. Undetermined values are
returned.
handling will not be executed correctly.
2
. The result might be a program runaway.
1
. There are three reasons for this.
PP
is applied.
PP
= 12 V))