HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 20

• Manufacturer Part Number: HD64F3048VTF8
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048VTF8

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F3048VX8

11.3 Operation .......................................................................................................................... 427
11.4 Usage Notes ...................................................................................................................... 434
Section 12 Watchdog Timer
12.1 Overview........................................................................................................................... 437
12.2 Register Descriptions ........................................................................................................ 439
12.3 Operation .......................................................................................................................... 445
12.4 Interrupts ........................................................................................................................... 448
12.5 Usage Notes ...................................................................................................................... 448
12.6 Notes ................................................................................................................................. 449
Rev. 7.00 Sep 21, 2005 page xviii of xxiv
11.2.1 Port A Data Direction Register (PADDR) ........................................................... 415
11.2.2 Port A Data Register (PADR).............................................................................. 415
11.2.3 Port B Data Direction Register (PBDDR) ........................................................... 416
11.2.4 Port B Data Register (PBDR) .............................................................................. 416
11.2.5 Next Data Register A (NDRA) ............................................................................ 417
11.2.6 Next Data Register B (NDRB)............................................................................. 419
11.2.7 Next Data Enable Register A (NDERA).............................................................. 421
11.2.8 Next Data Enable Register B (NDERB) .............................................................. 422
11.2.9 TPC Output Control Register (TPCR) ................................................................. 423
11.2.10 TPC Output Mode Register (TPMR) ................................................................... 425
11.3.1 Overview.............................................................................................................. 427
11.3.2 Output Timing...................................................................................................... 428
11.3.3 Normal TPC Output............................................................................................. 429
11.3.4 Non-Overlapping TPC Output ............................................................................. 431
11.3.5 TPC Output Triggering by Input Capture ............................................................ 433
11.4.1 Operation of TPC Output Pins ............................................................................. 434
11.4.2 Note on Non-Overlapping Output........................................................................ 434
12.1.1 Features................................................................................................................ 437
12.1.2 Block Diagram..................................................................................................... 438
12.1.3 Pin Configuration................................................................................................. 438
12.1.4 Register Configuration......................................................................................... 439
12.2.1 Timer Counter (TCNT)........................................................................................ 439
12.2.2 Timer Control/Status Register (TCSR)................................................................ 440
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 442
12.2.4 Notes on Register Access..................................................................................... 443
12.3.1 Watchdog Timer Operation ................................................................................. 445
12.3.2 Interval Timer Operation ..................................................................................... 446
12.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 446
12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 447
............................................................................................. 437