HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 642

• Manufacturer Part Number: HD64F3048VTF8
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048VTF8

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F3048VX8

Section 19 Flash Memory (H8/3048F: Dual Power Supply (V
Flowchart for Erasing Multiple Blocks
Rev. 7.00 Sep 21, 2005 page 616 of 878
REJ09B0259-0700
Erase-verify
next block
Address + 1
address
No
Select erase mode (E bit = 1 in FLMCR)
Figure 19.12 Multiple-Block Erase Flowchart
Clear EBR bit of erase-verified block
Wait initial value setting x = 6.25 ms
(set bits of blocks to be erased to 1)
Write 0 data to all addresses to be
No
Dummy write to verify address
(flash memory latches address)
Set top address of block as
(V
Set erase block registers
Enable watchdog timer
Select erase-verify mode
Disable watchdog timer
(EV bit = 1 in FLMCR)
(EBR1 = EBR2 = 0?)
PP
erased (prewrite)
All blocks erased?
Yes
address in block?
All erased blocks
Yes
Clear
E bit = 1 in FLMCR)
verify address
Wait (t
Wait (t
(read memory)
OK
Clear EV bit
End of erase
Set V
Yes
Wait (x) ms
Wait (z) µs
Clear E bit
verified?
Verify
Start
n = 1
Last
V
PP
VS1
VS2
PP
E bit
E
) s
) s
bit
*5
*5
*1
*2
*
3
No good
No
*4
Erasing ends
(clear bits of blocks to be erased to 0)
Double the erase time (x
All erased blocks
Notes: 1. Program all addresses to be erased by
Clear erase block registers
verified?
Yes
Clear
Yes
Erase error
2. Set the watchdog timer overflow interval to
3. For the erase-verify dummy write, write H'FF
4. When erasing two or more blocks, clear the
5. t
6. The erase time x is successively
n
n
N?
V
following the prewrite flowchart.
the value indicated in table 19.10.
with a byte transfer instruction.
bits of erased blocks in the erase block
register, so that only unerased blocks will be
erased again.
z:
t
N:
incremented by the initial set value
value of 10 ms or less should be
set, and the time for one erasure
should be 50 ms or less.
4?
PP
No
VS1
VS2
PP
2n
E
: 4 µs
: 2 s
= 12 V))
Erase-verify next block
–1
bit
5 to 10 s
602
(n = 1, 2, 3, 4). An initial
No
2
x)
No
*6
Yes
n + 1
n