HD64F3048VTF8 Renesas Electronics America, HD64F3048VTF8 Datasheet - Page 272

• Manufacturer Part Number: HD64F3048VTF8
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048VTF8

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F3048VX8

Section 8 DMA Controller
8.4.10
During a DMA transfer, if the bus right is requested by an external bus request signal (BREQ) or
by the refresh controller, the DMAC releases the bus after completing the transfer of the current
byte or word. If there is a transfer request at this point, the DMAC requests the bus right again.
Figure 8.20 shows an example of the timing of insertion of a refresh cycle during a burst transfer
on channel 0.
Rev. 7.00 Sep 21, 2005 page 246 of 878
REJ09B0259-0700
Address
bus
RD
HWR
LWR
Address
bus
RD
HWR LWR
,
,
External Bus Requests, Refresh Controller, and DMAC
DMAC cycle
(channel 1)
T
1
Figure 8.20 Bus Timing of Refresh Controller and DMAC
T
1
T
Figure 8.19 Timing of Multiple-Channel Operations
2
DMAC cycle (channel 0)
T
2
T
1
T
1
T
CPU
cycle
2
T
2
T
1
T
d
T
2
T
T
1
DMAC cycle
(channel 0A)
1
T
T
2
2
T
T
1
Refresh
cycle
1
T
T
2
2
T
T
1
d
CPU
cycle
T
T
DMAC cycle (channel 0)
1
2
T
T
2
d
T
T
1
1
DMAC cycle
(channel 1)
T
T
2
2
T
T
1
1
T
T
2
2