XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 111

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 73: DonePin and DriveDone Bitstream Option Interaction
M2, M1, M0: Configuration Mode Selection
The M2, M1, and M0 inputs select the FPGA configuration
mode, as described in
the mode pins are sampled on the rising edge of INIT_B.
Table 74: Spartan-3 Mode Select Settings
Before and during configuration, the mode pins have an inter-
nal pull-up resistor to VCCAUX, regardless of the HSWAP_EN
pin. If the mode pins are unconnected, then the FPGA defaults
to the Slave Serial configuration mode. After configuration suc-
cessfully completes, any levels applied to these input are
ignored. Furthermore, the bitstream generator options M0Pin,
M1Pin, and M2Pin determines whether a pull-up resistor,
pull-down resistor, or no resistor is present on its respective
mode pin, M0, M1, or M2.
HSWAP_EN: Disable Pull-up Resistors During
Configuration
As shown in
pull-up resistors on all user I/Os not actively involved in the
DS099-4 (v2.5) December 4, 2009
Product Specification
Notes:
1.
Master Serial
Slave Serial
Master Parallel
Slave Parallel
JTAG
Reserved
Reserved
Reserved
After Configuration
DonePin
Pullnone
Pullnone
Pullnone
Pullnone
Pullup
Pullup
Pullup
Pullup
Configuration Mode
X = don’t care, either 0 or 1.
Table
R
DriveDone
75, a Low on this asynchronous pin enables
Yes
Yes
Yes
Yes
No
No
No
No
Table
74. The logic levels applied to
Single- or Multi-
FPGA Design
M2
X
0
1
0
1
1
0
0
1
Single
Single
Single
Single
Multi
Multi
Multi
Multi
M1
X
0
1
1
1
0
0
1
0
External pull-up resistor, with value between 330Ω to 3.3kΩ , required on
DONE.
External pull-up resistor, with value between 330Ω to 3.3kΩ , required on
common node connecting to all DONE pins.
OK, no external requirements.
DriveDone on last device in daisy-chain only. No external requirements.
OK, but pull-up on DONE pin has slow rise time. May require 330Ω
pull-up resistor for high CCLK frequencies.
External pull-up resistor, with value between 330Ω to 3.3kΩ , required on
common node connecting to all DONE pins.
OK, no external requirements.
DriveDone on last device in daisy-chain only. No external requirements.
M0
X
0
1
1
0
1
1
0
0
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configuration process, although only until device configuration
completes. A High disables the pull-up resistors during config-
uration, which is the desired state for some applications.
The dedicated configuration CONFIG pins (CCLK, DONE,
PROG_B, HSWAP_EN, M2, M1, M0), the JTAG pins (TDI,
TMS, TCK, TDO) and the INIT_B always have active pull-up
resistors during configuration, regardless of the value on
HSWAP_EN.
After configuration, HSWAP_EN becomes a "don’t care" input
and any pull-up resistors previously enabled by HSWAP_EN
are disabled. If a user I/O in the application requires a pull-up
resistor after configuration, place a PULLUP primitive on the
associated I/O pin or, for some pins, set the associated bit-
stream generator option.
Table 75: HSWAP_EN Encoding
The Bitstream generator option HswapenPin determines
whether a pull-up resistor to VCCAUX, a pull-down resistor,
or no resistor is present on HSWAP_EN after configuration.
Notes:
1.
During Configuration
After Configuration, User Mode
HSWAP_EN
X = don’t care, either 0 or 1.
X
0
1
Spartan-3 FPGA Family: Pinout Descriptions
Comments
Enable pull-up resistors on all pins not
actively involved in the configuration
process. Pull-ups are only active until
configuration completes. See
No pull-up resistors during configuration.
This pin has no function except during
device configuration.
Function
Table
78.
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