XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 68

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 40: System-Synchronous Pin-to-Pin Setup and Hold Times for the IOB Input Path
68
Notes:
1.
2.
3.
4.
Setup Times
Hold Times
The numbers in this table are tested using the methodology presented in
forth in
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the
data Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from
add the appropriate Input adjustment from the same table.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the
data Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from
subtract the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data
before the clock’s active edge.
DCM output jitter is included in all measurements.
Symbol
T
T
T
T
PSDCM
PHDCM
PHFD
PSFD
Table 31
When writing to the Input
Flip-Flop (IFF), the time from the
setup of data at the Input pin to
the active transition at a Global
Clock pin. The DCM is in use. No
Input Delay is programmed.
When writing to IFF, the time
from the setup of data at the
Input pin to an active transition at
the Global Clock pin. The DCM is
not in use. The Input Delay is
programmed.
When writing to IFF, the time
from the active transition at the
Global Clock pin to the point
when data must be held at the
Input pin. The DCM is in use. No
Input Delay is programmed.
When writing to IFF, the time
from the active transition at the
Global Clock pin to the point
when data must be held at the
Input pin. The DCM is not in use.
The Input Delay is programmed.
and
Table
Description
34.
LVCMOS25
IOBDELAY = NONE,
with DCM
LVCMOS25
IOBDELAY = IFD,
without DCM
LVCMOS25
IOBDELAY = NONE,
with DCM
LVCMOS25
IOBDELAY = IFD,
without DCM
www.xilinx.com
Conditions
(4)
(4)
(2)
(2)
(3)
(3)
,
,
,
,
Table 47
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
and are based on the operating conditions set
Device
Table
Table
DS099-3 (v2.5) December 4, 2009
43. If this is true of the data Input,
43. If this is true of the data Input,
–0.45
–0.12
–0.12
–0.43
–0.45
–0.47
–0.61
–0.62
–0.98
–0.40
–0.27
–1.19
–1.43
–2.33
–2.47
–2.66
2.37
2.13
2.15
2.58
2.55
2.59
2.76
2.69
3.00
2.63
2.50
3.50
3.78
4.98
5.25
5.37
Min
-5
Speed Grade
Product Specification
–0.40
–0.05
–0.05
–0.38
–0.40
–0.42
–0.56
–0.57
–0.93
–0.35
–0.22
–1.14
–1.38
–2.28
–2.42
–2.61
2.71
2.35
2.36
2.95
2.91
2.96
3.15
3.08
3.46
3.02
2.87
4.03
4.35
5.73
6.05
6.18
Min
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R