XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 127

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CP132: 132-Ball Chip-Scale Package
Note: The CP132 and CPG132 packages are being discontinued
and are not recommended for new designs. See
inx.com/support/documentation/spartan-3.htm#19600 for the
latest
The XC3S50 is available in the 132-ball chip-scale package,
CP132. The pinout and footprint for this package appear in
Table 88
All the package pins appear in
bank number, then by pin name. Pins that form a differential
I/O pair appear together in the table. The table also shows
the pin number for each pin and the pin type, as defined ear-
lier.
The CP132 footprint has eight I/O banks. However, the volt-
age supplies for the two I/O banks along an edge are con-
nected together internally. Consequently, there are four
output
VCCO_RIGHT, VCCO_BOTTOM, and VCCO_LEFT.
Pinout Table
Table 88: CP132 Package Pinout
DS099-4 (v2.5) December 4, 2009
Product Specification
Bank
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
updates.
and
voltage
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L27N_0
IO_L27P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L27N_1
IO_L27P_1
IO_L28N_1
IO_L28P_1
IO_L31N_1/VREF_1
IO_L31P_1
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L20N_2
IO_L20P_2
IO_L21N_2
R
Figure
XC3S50 Pin Name
44.
supplies,
Table 88
labeled
CP132
and are sorted by
Ball
C11
D12
C14
A13
B13
A12
A11
B11
A10
E12
E13
E14
C4
C5
C7
C8
C9
A3
B5
B6
A6
B7
A7
A8
A9
VCCO_TOP,
VREF
GCLK
GCLK
VREF
GCLK
GCLK
www.xil-
Type
DCI
DCI
DCI
DCI
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
www.xilinx.com
Table 88: CP132 Package Pinout
Bank
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
6
6
Spartan-3 FPGA Family: Pinout Descriptions
IO_L21P_2
IO_L23N_2/VREF_2
IO_L23P_2
IO_L24N_2
IO_L24P_2
IO_L40N_2
IO_L40P_2/VREF_2
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L20N_3
IO_L20P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3/VREF_3
IO_L24N_3
IO_L24P_3
IO_L40N_3/VREF_3
IO_L40P_3
IO/VREF_4
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L30N_4/D2
IO_L30P_4/D3
IO_L31N_4/INIT_B
IO_L31P_4/DOUT/BUSY
IO_L32N_4/GCLK1
IO_L32P_4/GCLK0
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
IO_L27N_5/VREF_5
IO_L27P_5
IO_L28N_5/D6
IO_L28P_5/D7
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
XC3S50 Pin Name
CP132
Ball
G12
G13
G14
H12
N13
N14
M14
H14
N12
M11
M10
N10
F12
F13
F14
K13
K12
K14
P12
L12
L14
L13
J12
J13
N9
M8
N8
M7
N2
M4
N4
M6
M1
P9
P8
P2
P3
P4
P5
P7
P6
L3
VREF
VREF
VREF
VREF
VREF
GCLK
GCLK
VREF
GCLK
GCLK
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
Type
DCI
DCI
DCI
DCI
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
127