XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 59

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 32: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins (Continued)
DS099-3 (v2.5) December 4, 2009
Product Specification
98
Notes:
1.
2.
3.
Symbol
R
R
I
C
PD
REF
The numbers in this table are based on the conditions set forth in
The I
minimum and maximum values
within this range before applying V
the ESD protection diodes, shown in Module 2:
impedance, but there is a path through the upper and lower ESD protection diodes.
This parameter is based on characterization. The pull-up resistance R
Spartan-3 family values for both resistances are stronger than they have been for previous FPGA families.
DCI
IN
(3)
L
specification applies to every I/O pin throughout power-on as long as the voltage on that pin stays between the absolute V
Equivalent resistance of pull-down resistor
at User I/O, Dual-Purpose, and Dedicated
pins, driven from I
Value of external reference resistor to
support DCI I/O standards
V
Input capacitance
R
REF
current per pin
Description
RPD
(Table
CCO
27). For hot-swap applications, at the time of card connection, be sure to keep all I/O voltages
power. Consider applying V
Spartan-3 FPGA Family: DC and Switching Characteristics
Figure 5, page
www.xilinx.com
V
V
V
V
V
IN
IN
IN
IN
IN
=V
=V
=V
=V
=V
Test Conditions
13. When the FPGA is completely unpowered, the I/O pins are high
CCO
CCO
V
V
CCO
CCO
CCO
Table
CCO
CCO
CCO
= 3.0V to 3.465V
= 1.14 to 1.26V
= 2.3V to 2.7V
= 1.7V to 1.9V
= 1.4V to 1.6V
PU
power before connecting the signal lines, to avoid turning on
> 3.0V
< 3.0V
31.
= V
CCO
/ I
RPU
. The pull-down resistance R
1.75
1.35
1.00
0.85
0.68
Min
20
3
-
-
Typ
-
-
-
-
-
-
-
-
-
3.465
Max
9.35
7.30
5.15
4.35
±
±
100
10
PD
25
10
= V
IN
Units
/ I
kΩ
kΩ
kΩ
kΩ
kΩ
μA
μA
pF
Ω
RPD
IN
59
.