XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 66

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Spartan-3 FPGA Family: DC and Switching Characteristics
Switching Characteristics
All Spartan-3 devices are available in two speed grades: –4
and the higher performance –5. Switching characteristics in
this document may be designated as Advance, Preliminary,
or Production. Each category is defined as follows:
Advance: These specifications are based on simulations
only and are typically available soon after establishing
FPGA specifications. Although speed grades with this des-
ignation are considered relatively stable and conservative,
some under-reported delays may still occur.
Preliminary: These specifications are based on complete
early silicon characterization. Devices and speed grades
with this designation are intended to give a better indication
of the expected performance of production silicon. The
probability of under-reporting preliminary delays is greatly
reduced compared to Advance data.
Production: These specifications are approved once
enough production silicon of a particular device family mem-
ber has been characterized to provide full correlation
between speed files and devices over numerous production
lots. There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes. Typ-
ically, the slowest speed grades transition to Production
before faster speed grades.
Production-quality systems must use FPGA designs com-
piled using a Production status speed file. FPGAs designs
using a less mature speed file designation may only be
used during system prototyping or preproduction qualifica-
tion. FPGA designs using Advance or Preliminary status
speed files should never be used in a production-quality
system.
Whenever a speed file designation changes, as a device
matures toward Production status, rerun the Xilinx ISE soft-
ware on the FPGA design to ensure that the FPGA design
incorporates the latest timing information and software
updates.
•
66
Xilinx ISE Software Updates
http://www.xilinx.com/support/download/index.htm
www.xilinx.com
All specified limits are representative of worst-case supply
voltage and junction temperature conditions. Unless other-
wise noted, the following applies: Parameter values apply to
all Spartan-3 devices. All parameters representing voltages
are measured with respect to GND.
Selected timing parameters and their representative values
are included below either because they are important as
general design requirements or they indicate fundamental
device performance characteristics. The Spartan-3 v1.38
speed files are the original source for many but not all of the
values. The v1.38 speed files are available in Xilinx Inte-
grated Software Environment (ISE) software version 8.2i.
The speed grade designations for these files are shown in
Table
data, use the values reported by the Xilinx static timing ana-
lyzer (TRACE in the Xilinx development software) and
back-annotated to the simulation netlist.
Table 38: Spartan-3 Speed Grade Designations (ISE
v8.2i or later)
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Device
38. For more complete, more precise, and worst-case
Advance
DS099-3 (v2.5) December 4, 2009
Preliminary
Product Specification
Production
(v1.37 and
(v1.38 and
–4, –5
–4, –5
later)
later)
R