XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 124

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Spartan-3 FPGA Family: Pinout Descriptions
VQ100: 100-lead Very-thin Quad Flat
Package
The XC3S50 and the XC3S200 devices are available in the
100-lead very-thin quad flat package, VQ100. Both devices
share a common footprint for this package as shown in
Table 86
All the package pins appear in
bank number, then by pin name. Pairs of pins that form a dif-
ferential I/O pair appear together in the table. The table also
shows the pin number for each pin and the pin type, as
defined earlier.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web-
site at
sheets/s3_pin.zip
Pinout Table
Table 86: VQ100 Package Pinout
124
Bank
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
3
3
http://www.xilinx.com/support/documentation/data_
and
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L31N_0
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
VCCO_0
IO
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L31N_1/VREF_1
IO_L31P_1
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
VCCO_1
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L21N_2
IO_L21P_2
IO_L24N_2
IO_L24P_2
IO_L40N_2
IO_L40P_2/VREF_2
VCCO_2
IO
IO
Figure
.
Pin Name
XC3S200
42.
XC3S50
Table 86
VQ100 Pin
Number
and are sorted by
P97
P96
P92
P91
P90
P89
P94
P81
P80
P79
P86
P85
P88
P87
P83
P75
P74
P72
P71
P68
P67
P65
P64
P70
P55
P59
VCCO
VCCO
VCCO
GCLK
GCLK
GCLK
GCLK
VREF
VREF
VREF
Type
DCI
DCI
DCI
DCI
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
www.xilinx.com
Table 86: VQ100 Package Pinout
Bank
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
7
7
7
7
7
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L24N_3
IO_L24P_3
IO_L40N_3/VREF_3
IO_L40P_3
VCCO_3
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L30N_4/D2
IO_L30P_4/D3
IO_L31N_4/INIT_B
IO_L31P_4/DOUT/BUSY
IO_L32N_4/GCLK1
IO_L32P_4/GCLK0
VCCO_4
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
IO_L28N_5/D6
IO_L28P_5/D7
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
VCCO_5
IO
IO
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
IO_L24N_6/VREF_6
IO_L24P_6
IO_L40N_6
IO_L40P_6/VREF_6
VCCO_6
IO_L01N_7/VRP_7
IO_L01P_7/VRN_7
IO_L21N_7
IO_L21P_7
IO_L23N_7
Pin Name
XC3S200
XC3S50
DS099-4 (v2.5) December 4, 2009
VQ100 Pin
Product Specification
Number
P54
P53
P61
P60
P63
P62
P57
P50
P49
P48
P47
P44
P43
P42
P40
P39
P38
P46
P28
P27
P32
P30
P35
P34
P37
P36
P31
P17
P21
P23
P22
P16
P15
P14
P13
P19
P2
P1
P5
P4
P9
VCCO
VCCO
VCCO
VCCO
VREF
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
GCLK
GCLK
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
GCLK
GCLK
VREF
VREF
Type
DCI
DCI
DCI
DCI
DCI
DCI
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R