XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 89

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 60: Switching Characteristics for the DFS
Notes:
1.
2.
3.
4.
5.
DS099-3 (v2.5) December 4, 2009
Product Specification
98
Output Frequency Ranges
CLKOUT_FREQ_FX_LF
CLKOUT_FREQ_FX_HF
Output Clock Jitter
CLKOUT_PER_JITT_FX
Duty Cycle
CLKOUT_DUTY_CYCLE_FX
Phase Alignment
CLKOUT_PHASE
Lock Time
LOCK_DLL_FX
LOCK_FX
The numbers in this table are based on the operating conditions set forth in
Mask revisions prior to the E mask revision have a CLKOUT_FREQ_FX_HF max of 280 MHz. See
Use the DCM Clocking Wizard in the ISE software for a Spartan-3 device specific number. Jitter number assumes 150 ps of input clock jitter.
The CLKFX and CLKFX180 outputs always approximate 50% duty cycles.
DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) is in use.
Symbol
(4)
R
Frequency for the CLKFX and CLKFX180
outputs
Period jitter at the CLKFX and CLKFX180
outputs
Duty cycle precision for the CLKFX and
CLKFX180 outputs
Phase offset between the DFS output and
the CLK0 output
When using the DFS in conjunction with the
DLL: The time from deassertion at the DCM’s
Reset input to the rising transition at its
LOCKED output. When the DCM is locked,
the CLKIN and CLKFB signals are in phase.
When using the DFS without the DLL: The
time from deassertion at the DCM’s Reset
input to the rising transition at its LOCKED
output. By asserting the LOCKED signal, the
DFS indicates valid CLKFX and CLKFX180
signals.
Description
Spartan-3 FPGA Family: DC and Switching Characteristics
www.xilinx.com
Frequency
Table 31
Mode
High
Low
All
All
All
All
All
and
Table
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Device
All
All
All
All
All
All
59.
Mask and Fab Revisions, page
Note 3
Min
210
18
-
-
-
-
-
-
-
-
-
-
-
-5
Note 3
326
±
±
±
±
±
±
±
±
±
Speed Grade
Max
10.0
10.0
210
100
100
250
400
400
400
400
400
300
(2)
Note 3
Min
210
18
-
-
-
-
-
-
-
-
-
-
-
-4
Note 3
307
±
±
±
±
±
±
±
±
±
55.
Max
10.0
10.0
210
100
100
250
400
400
400
400
400
300
(2)
Units
MHz
MHz
ms
ms
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
89