XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 159

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

User I/Os by Bank
Table 100
tributed between the eight I/O banks for the XC3S400 in the
FG456 package. Similarly,
Table 100: User I/Os Per Bank for XC3S400 in FG456 Package
Table 101: User I/Os Per Bank for XC3S1000, XC3S1500, and XC3S2000 in FG456 Package
DS099-4 (v2.5) December 4, 2009
Product Specification
Bottom
Bottom
Edge
Edge
Right
Right
Left
Left
Top
Top
indicates how the available user-I/O pins are dis-
R
I/O Bank
Bank
I/O
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Table 101
Maximum
Maximum
I/O
I/O
35
35
31
31
35
35
31
31
40
40
43
43
41
40
43
43
shows how the avail-
I/O
I/O
27
27
25
25
21
21
25
25
31
31
37
37
26
25
37
37
www.xilinx.com
able user-I/O pins are distributed between the eight I/O
banks for the XC3S1000, XC3S1500, and XC3S2000 in the
FG456 package.
DUAL
DUAL
0
0
0
0
6
6
0
0
0
0
0
0
6
6
0
0
All Possible I/O Pins by Type
All Possible I/O Pins by Type
Spartan-3 FPGA Family: Pinout Descriptions
DCI
DCI
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
VREF
VREF
4
4
4
4
4
4
4
4
5
5
4
4
5
5
4
4
GCLK
GCLK
2
2
0
0
2
2
0
0
2
2
0
0
2
2
0
0
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