XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 98

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Spartan-3 FPGA Family: DC and Switching Characteristics
98
04/26/06
05/25/07
11/30/07
06/25/08
12/04/09
Date
Version No.
2.1
2.2
2.3
2.4
2.5
Updated document links.
Improved absolute maximum voltage specifications in
allowance. Improved XC3S50 HBM ESD to 2000V in
data, improved (reduced) the maximum quiescent current limits for the I
in
footnote in
in
Updated 3.3V VCCO max from 3.45V to 3.465V in
0.50μs to 0.25μs in
Clarified dual marking. Added
Table
values. Added HSLVDCI to
value in speed file. Updated formatting and links.
Updated notes 2 and 3 in
Table
V
in
Table
being discontinued in
Updated footnote 3 in
Removed silicon process specific information and revised notes in
(PS).
OL
Table
Table
Figure
max and V
31. Removed absolute minimum and added footnote referring to timing analyzer for minimum delay
29. Updated note 3 in
47. Updated
33. Widened the recommended voltage range for the PCI standard and clarified the hysteresis
63.
37. Updated V
Table
OH
34. Noted restriction on combining differential outputs in
min for SSTL2_II in
Simultaneously Switching Output
Table
Table
Table
ICM
64. Updated links to technical documentation.
Table
48. Removed minimum values for T
Table 47
www.xilinx.com
max for LVPECL_25 in
Table
57. Removed minimum values for T
Mask and Fab
27. Removed silicon process specific information and revised notes in
31. Updated note 3 in
and
Table
Table
35. Updated note 5 in
Description
Revisions. Added references to
49. Updated t
Table 31
Table
Table
Table
Guidelines. Noted that the CP132 package is
Table
36. Updated RT and VT for LVDS_25_DCI in
and elsewhere. Reduced t
27. Based on extensive 90 nm production
27, providing additional overshoot
DICK
33. Updated note 5 in
MULTCK
MULT
in
Table
Table
Table 50
propagation times in
DS099-3 (v2.5) December 4, 2009
clock-to-output times in
CCINTQ
35. Updated JTAG Waveforms
60. Updated
Table
to match largest possible
XAPP459
and I
37. Updated footnote 1
Product Specification
CCOQ
ICCK
Table
Phase Shifter
in
minimum from
specifications
Table 27
Table
34. Updated
Table
54.
and
53.
R