XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 86

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Spartan-3 FPGA Family: DC and Switching Characteristics
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital Fre-
quency Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM applica-
tions. All such applications inevitably use the CLKIN and the
CLKFB inputs connected to either the CLK0 or the CLK2X
feedback, respectively. Thus, specifications in the DLL
tables
only employs the DLL component. When the DFS and/or
the PS components are used together with the DLL, then
the specifications listed in the DFS and PS tables
through
DLL tables. DLL specifications that do not change with the
Delay-Locked Loop (DLL)
Table 57: Recommended Operating Conditions for the DLL
Notes:
1.
2.
3.
4.
5.
86
Input Frequency Ranges
F
Input Pulse Requirements
CLKIN_PULSE
Input Clock Jitter Tolerance and Delay Path Variation
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_DLL_HF
CLKIN_PER_JITT_DLL_LF
CLKIN_PER_JITT_DLL_HF
CLKFB_DELAY_VAR_EXT
CLKIN
DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
The DFS, when operating independently of the DLL, supports lower F
The CLKIN_DIVIDE_BY_2 attribute can be used to increase the effective input frequency range up to F
CLKIN_DIVIDE_BY_2 divides the incoming clock frequency by two as it enters the DCM.
Industrial temperature range devices have additional requirements for continuous clocking, as specified in
CLKIN input jitter beyond these limits may cause the DCM to lose lock. See
(Table 57
Table
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_DLL_HF
Symbol
62) supersede any corresponding ones in the
and
Table
58) apply to any application that
Frequency for the CLKIN input
CLKIN pulse width as a
percentage of the CLKIN period
Cycle-to-cycle jitter at the CLKIN
input
Period jitter at the CLKIN input
Allowable variation of off-chip
feedback delay from the DCM
output to the CLKFB input
Description
(Table 59
(4)
www.xilinx.com
addition of DFS or PS functions are presented in
and
Period jitter and cycle-cycle jitter are two (of many) different
ways of characterizing clock jitter. Both specifications
describe statistical variation from a mean value.
Period jitter is the worst-case deviation from the average
clock period of all clock cycles in the collection of clock peri-
ods sampled (usually from 100,000 to more than a million
samples for specification purposes). In a histogram of
period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period
between adjacent clock cycles in the collection of clock peri-
ods sampled. In a histogram of cycle-cycle jitter, the mean
value is zero.
Frequency Mode/
F
F
CLKIN
CLKIN
F
CLKIN
Table
CLKIN
High
High
Low
Low
< 100 MHz
> 100 MHz
All
All
frequencies. See
UG331
Range
58.
for more details.
18
40%
45%
Min
48
-
-
-
-
(2)
Table
-5
DS099-3 (v2.5) December 4, 2009
167
280
±
±
Max
60%
55%
Speed Grade
±
±
59.
300
150
1
1
(3)
(3)
BUFG
Table
18
40%
45%
Min
48
. When set to TRUE,
Product Specification
-
-
-
-
(2)
63.
-4
280
167
±
±
Max
60%
55%
±
±
300
150
(3,4)
1
1
(3)
Table 57
Units
MHz
MHz
ps
ps
ns
ns
-
-
R