XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 97

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision History
DS099-3 (v2.5) December 4, 2009
Product Specification
98
04/11/03
07/11/03
02/06/04
03/04/04
08/24/04
12/17/04
08/19/05
04/03/06
Date
R
Version No.
1.0
1.1
1.2
1.3
1.4
1.5
1.6
2.0
Initial Xilinx release.
Extended Absolute Maximum Rating for junction temperature in
quiescent supply current
Revised V
number
current numbers
LVDCI_DV2 and LVPECL standards
Table
Added timing numbers from v1.29 speed files as well as DCM timing
Added reference to errata documents on
information
(Table
(Table
(Table
V
(Table 39
Updated DCM timing with latest characterization data
pulse width specification
Improved DCM PSCLK pulse width specification
(Table
removed BitGen command table and referring text. Adjusted maximum CCLK frequency for the slave
serial and parallel configuration modes
setup times
Updated timing parameters to match v1.35 speed file. Improved V
Added a note limiting the rate of change of V
the XC3S2000, XC3S4000, and XC3S5000
standards
guidelines for the FT and FG packages
using compressed bitstreams
(Table
Updated timing parameters to match v1.37 speed file. All Spartan-3 part types, except XC3S5000,
promoted to Production status. Removed V
devices
(Table
(Table
values
18 MHz
(Table
Industrial temperature range applications. Updated
Table 49
SDRAM interfaces. Added differential (or complementary single-ended) DIFF_HSTL_II_18 and
DIFF_SSTL2_II I/O standards, including DCI terminated versions. Added electro-static discharge (ESD)
data for the XC3S2000 and larger FPGAs
receive automatic notifications of data sheet or errata changes.
Upgraded Module 3, removing Preliminary status. Moved XC3S5000 to Production status in
Finalized I/O timing on XC3S5000 for v1.38 speed files. Added minimum timing values for various logic
and I/O paths. Corrected labels for R
mask revision ‘E’ specifications for LVDS_25, RSDS_25, LVDSEXT_25 differential outputs to
Added BLVDS termination requirements to
Outputs (SSOs) limits in
on a printed circuit board. Updated Note 2 in
minimum pulse width specification, T
OL
levels for differential standards
66).
32). Updated quiescent current numbers and added information on power-on and surplus current
33). Adjusted V
34). Added note limiting V
62). Because the BitGen option Centered_x#_y# is not necessary for Variable Phase Shift mode,
34,
32). Added worst-case quiescent current values for XC3S2000, XC3S4000, XC3S5000
33). Added industrial temperature range specification and improved typical quiescent current
59,
(Table
(Table
(Table
(Table
for QFP packages. Added information on SSTL18_II I/O standard and timing to support DDR2
through
IN
(Table
Table
Table
(Table
(Table
maximum rating
33). Improved the DLL minimum clock input frequency specification from 24 MHz down to
32), and differential output voltage levels
29). Added equivalent resistance values for internal pull-up and pull-down resistors
57). Improved the DFS minimum and maximum clock output frequency specifications
35,
60). Added new miscellaneous DCM specifications
(Table
35). Added SSO guidelines for the VQ, TQ, and PQ packages as well as edited SSO
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 47
27). Explained V
67).
Table
REF
33). Updated pull-up and pull-down resistor strengths
Table 49
(Table
(Table
43,
range for HSTL_III and HSTL_I_18 and changed V
and
www.xilinx.com
(Table
(Table 65
Table
Table 50
57). Recommended use of Virtex-II FPGA Jitter calculator
33) and DLL timing.
TT
for quad-flat packaged based on silicon testing using devices soldered
CCO
range for SSTL2_II signal standards
(Table
46,
27). Added power-on requirements
PU
(Table 36
INIT
(Table
(Table
and R
and
Table
ramp time measurement
, to
page
through
(Table
37). Updated Switching Characteristics with speed file v1.32
CCO
Figure
CCAUX
(Table
Table
Table
Description
PD
Table
65). Inverted CCLK waveform
49). Added maximum CCLK frequencies for configuration
47, and
and
55. Clarified Absolute Maximum Ratings and added ESD
ramp rate restriction from all mask revision ‘E’ and later
and updated R
(Table
27). Added link to Spartan-3 errata notices and how to
Table
64.
66). Added specifications for the HSLVDCI standards
32. Improved recommended Simultaneous Switching
(Table
33). Increased I
Simultaneously Switching Output Guidelines
Table
62. Updated Note 6 in
(Table 57
Table
61). Changed Phase Shifter lock time parameter
55). Corrected IOB test conditions
(Table
37). Changed CCLK setup time
31). Added typical quiescent current values for
49).
through
37) for Rev. 0. Published new quiescent
PD
Table
CCO
(Table
conditions for in
OH
(Table
ramp time specification
(Table 57
and I
27. Added numbers for typical
Table
(Table
29). Clarified I
(Table
Table
OL
63), primarily affecting
(Figure
61). Improved DCM CLKIN
IH
for SSTL2-I and SSTL2-II
(Table
29), leakage current
35). Calculated V
through
min for LVCMOS12
29. Added INIT_B
Table
35). Adjusted JTAG
32). Added
L
Table
specification
32. Added final
(Table 65
(Table
(Table
(Table
Table
Table
62).
OH
40).
60).
38.
and
and
29).
and
37.
97