XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 54

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Spartan-3 FPGA Family: Functional Description
Revision History
54
54
04/11/03
05/19/03
07/11/03
08/24/04
08/19/05
04/03/06
04/26/06
05/25/07
11/30/07
06/25/08
12/04/09
Date
Version No.
1.0
1.1
1.2
1.3
1.4
2.0
2.1
2.2
2.3
2.4
2.5
Initial Xilinx release
Added Block RAM column, DCMs, and multipliers to XC3S50 descriptions.
Explained the configuration port Persist option in
Figure 6
the same as that for all other Spartan-3 devices. Updated description of I/O voltage tolerance in
Protection
to None. Added additional flexibility for making DLL connections in
the
interface, including guidelines for achieving 3.3V-tolerance.
Showed inversion of 3-state signal
(Table 5
output buffer name in
Corrected description of WRITE_FIRST and READ_FIRST in
setup and hold time requirements whenever a block RAM port is enabled
in the maximum length of a
Configuration Interface
information on CCLK behavior and termination recommendations to Configuration. Added
Configuration Details
Figure 29
Updated
supply voltage name and value in
Free-Running
Added more information on the pull-up resistors that are active during configuration to Configuration.
Added information to
JTAG if the mode select pins are set for other than JTAG.
Added
Added note that pull-down is active during boundary scan tests.
Updated links to documentation on xilinx.com.
Added HSLVDCI to
Updated HSLVDCI description in
differential signaling V
Organization of IOBs into
version requirement in
Configuration
Design Documentation
and
and
Figure
because its timing is not programmable.
section. In
page
Double-Data-Rate Transmission
Oscillators. Corrected a few minor typographical errors.
5. Updated
15). Added information on operating block RAM with multipliers to
section, inserted an explanation of how to choose power supplies for the configuration
Table
Figure
Boundary-Scan (JTAG) Mode
CCO
Table
The Fixed Phase
section. Added
section. Added information on the STATUS[2] DCM output
9. Updated formatting and links.
values in
www.xilinx.com
Configuration
Figure
Banks. Updated rule 4 in
9, changed input termination type for DCI version of the LVCMOS standard
19. Corrected description of how DOUT is synchronized to CCLK
Available. Noted SSTL2_I_DCI 25-Ohm driver in
Digitally Controlled Impedance
Figure 24
(Figure
12. Updated
Table
Powering Spartan-3 FPGAs
Mode.
9. Noted that the CP132 package is being discontinued in
5). Clarified description of pull-up and pull-down resistors
daisy-chain. Added reference to
and
Description
section to indicate that DDR clocking for the XC3S50 is
Table
Figure
Slave Parallel Mode (SelectMAP)
about potential interactions when configuring via
9. Updated
Rules Concerning
26. Added
Table
Figure
Figure 19
No Internal Charge Pumps or
(DCI). Updated the low-voltage
12. Added note regarding address
section. Removed GSR from
DS099-2 (v2.5) December 4, 2009
20. Corrected Platform Flash
(Table
Banks. Added software
XAPP453
and accompanying text. In
12). Added information
Product Specification
Table 9
page
(Table
section. Updated
in
3.3V-Tolerant
25. Corrected
and
22). Added
Additional
(page
Table
ESD
The
46).
10.
R