XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 182

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Spartan-3 FPGA Family: Pinout Descriptions
FG900: 900-lead Fine-pitch Ball Grid
Array
The 900-lead fine-pitch ball grid array package, FG900,
supports three different Spartan-3 devices, including the
XC3S2000, the XC3S4000, and the XC3S5000. The foot-
prints for the XC3S4000 and XC3S5000 are identical, as
shown in
ever, has fewer I/O pins which consequently results in 68
unconnected pins on the FG900 package, labeled as “N.C.”
In
indicated with a black diamond symbol ( ).
All the package pins appear in
bank number, then by pin name. Pairs of pins that form a dif-
ferential I/O pair appear together in the table. The table also
shows the pin number for each pin and the pin type, as
defined earlier.
If there is a difference between the XC3S2000 pinout and
the pinout for the XC3S4000 and XC3S5000, then that dif-
ference is highlighted in
shaded, then there is an unconnected pin on the XC3S2000
that maps to a user-I/O pin on the XC3S4000 and
XC3S5000.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web-
site at
sheets/s3_pin.zip
Pinout Table
Table 106: FG900 Package Pinout
182
Bank
Table 106
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
http://www.xilinx.com/support/documentation/data_
Table 106
IO
IO
IO
IO
IO
IO/VREF_0
IO/VREF_0
IO_L01N_0/
VRP_0
IO_L01P_0/
VRN_0
IO_L02N_0
IO_L02P_0
IO_L03N_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0
XC3S2000
Pin Name
and
.
Figure
and
IO
IO
IO
IO
IO
IO/VREF_0
IO/VREF_0
IO_L01N_0/
VRP_0
IO_L01P_0/
VRN_0
IO_L02N_0
IO_L02P_0
IO_L03N_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0
Figure
50, these unconnected pins are
Table
XC3S4000
XC3S5000
Pin Name
Table 106
50. The XC3S2000, how-
106. If the table entry is
Number
FG900
and are sorted by
D13
E15
K15
K13
Pin
G8
C4
D5
C6
F9
B4
A4
B5
A5
E6
B6
F6
VREF
VREF
Type
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
www.xilinx.com
Table 106: FG900 Package Pinout (Continued)
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L05P_0/
VREF_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0
IO_L12P_0
IO_L13N_0
IO_L13P_0
IO_L14N_0
IO_L14P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0
IO_L17P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0
IO_L19P_0
IO_L20N_0
IO_L20P_0
IO_L21N_0
IO_L21P_0
IO_L22N_0
IO_L22P_0
IO_L23N_0
IO_L23P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0
IO_L25P_0
IO_L26N_0
IO_L26P_0/
VREF_0
XC3S2000
Pin Name
IO_L05P_0/
VREF_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0
IO_L12P_0
IO_L13N_0
IO_L13P_0
IO_L14N_0
IO_L14P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0
IO_L17P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0
IO_L19P_0
IO_L20N_0
IO_L20P_0
IO_L21N_0
IO_L21P_0
IO_L22N_0
IO_L22P_0
IO_L23N_0
IO_L23P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0
IO_L25P_0
IO_L26N_0
IO_L26P_0/
VREF_0
XC3S4000
XC3S5000
Pin Name
DS099-4 (v2.5) December 4, 2009
Product Specification
Number
FG900
G10
C10
H11
G11
D11
C11
H12
G12
D12
C12
H13
F10
B10
K11
F11
E11
B11
A11
K12
F12
E12
B12
A12
F13
E13
B13
A13
K14
Pin
J10
J12
J13
J14
D7
C7
D8
C8
H9
F7
F8
E8
B8
A8
J9
VREF
VREF
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R