XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 83
XC3S200-4TQG144I
Manufacturer Part Number
XC3S200-4TQG144I
Description
FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S200-4TQG144I
Package
144TQFP
Family Name
Spartan®-3
Device Logic Units
4320
Device System Gates
200000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
97
Ram Bits
221184
Package / Case
144-TQFP, 144-VQFP
Mounting Type
Surface Mount
Voltage - Supply
1.14 V ~ 3.465 V
Operating Temperature
-40°C ~ 100°C
Number Of I /o
97
Number Of Logic Elements/cells
*
Number Of Gates
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
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Price
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Part Number:
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Table 51: CLB Distributed RAM Switching Characteristics
Table 52: CLB Shift Register Switching Characteristics
DS099-3 (v2.5) December 4, 2009
Product Specification
98
Clock-to-Output Times
Setup Times
Hold Times
Clock Pulse Width
Clock-to-Output Times
Setup Times
Hold Times
Clock Pulse Width
T
T
T
DH,
WPH
WPH
Symbol
Symbol
T
T
T
T
SHCKO
SRLDS
SRLDH
T
T
T
T
REG
AH,
WS
AS
DS
, T
, T
WPL
WPL
T
R
WH
Time from the active edge at the CLK input to data
appearing on the distributed RAM output
Setup time of data at the BX or BY input before the active
transition at the CLK input of the distributed RAM
Setup time of the F/G address inputs before the active
transition at the CLK input of the distributed RAM
Setup time of the write enable input before the active
transition at the CLK input of the distributed RAM
Hold time of the BX, BY data inputs, the F/G address
inputs, or the write enable input after the active transition
at the CLK input of the distributed RAM
Minimum High or Low pulse width at CLK input
Time from the active edge at the CLK input to data
appearing on the shift register output
Setup time of data at the BX or BY input before the active
transition at the CLK input of the shift register
Hold time of the BX or BY data input after the active
transition at the CLK input of the shift register
Minimum High or Low pulse width at CLK input
Description
Description
Spartan-3 FPGA Family: DC and Switching Characteristics
www.xilinx.com
0.46
0.46
0.33
0.85
0.46
0.85
Min
Min
0
0
-
-
-5
-5
Max
1.87
Max
3.30
-
-
-
-
-
-
-
-
0.52
0.53
0.37
0.97
0.52
0.97
Min
Min
0
0
-
-
-4
-4
Max
2.15
Max
3.79
-
-
-
-
-
-
-
-
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
83
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