XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 131

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TQ144: 144-lead Thin Quad Flat
Package
The XC3S50, the XC3S200, and the XC3S400 are avail-
able in the 144-lead thin quad flat package, TQ144. All
devices share a common footprint for this package as
shown in
The TQ144 package only has four separate VCCO inputs,
unlike the BGA packages, which have eight separate VCCO
inputs. The TQ144 package has a separate VCCO input for
the top, bottom, left, and right. However, there are still eight
separate I/O banks, as shown in
Banks 0 and 1 share the VCCO_TOP input, Banks 2 and 3
share the VCCO_RIGHT input, Banks 4 and 5 share the
VCCO_BOTTOM input, and Banks 6 and 7 share the
VCCO_LEFT input.
All the package pins appear in
bank number, then by pin name. Pairs of pins that form a dif-
ferential I/O pair appear together in the table. The table also
shows the pin number for each pin and the pin type, as
defined earlier.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web-
site at
sheets/s3_pin.zip
Pinout Table
Table 90: TQ144 Package Pinout
DS099-4 (v2.5) December 4, 2009
Product Specification
Bank
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
http://www.xilinx.com/support/documentation/data_
Table 90
R
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L27N_0
IO_L27P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
IO
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L28N_1
IO_L28P_1
IO_L31N_1/VREF_1
IO_L31P_1
IO_L32N_1/GCLK5
.
and
Pin Name
XC3S200
XC3S400
XC3S50
Figure
44.
Table 90
Table 90
TQ144 Pin
Number
P141
P140
P137
P135
P132
P131
P130
P129
P128
P127
P116
P113
P112
P119
P118
P123
P122
P125
and are sorted by
and
Figure
GCLK
GCLK
GCLK
VREF
VREF
Type
DCI
DCI
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
www.xilinx.com
44.
Table 90: TQ144 Package Pinout (Continued)
Bank
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
5
Spartan-3 FPGA Family: Pinout Descriptions
IO_L32P_1/GCLK4
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L20N_2
IO_L20P_2
IO_L21N_2
IO_L21P_2
IO_L22N_2
IO_L22P_2
IO_L23N_2/VREF_2
IO_L23P_2
IO_L24N_2
IO_L24P_2
IO_L40N_2
IO_L40P_2/VREF_2
IO
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L20N_3
IO_L20P_3
IO_L21N_3
IO_L21P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3/VREF_3
IO_L24N_3
IO_L24P_3
IO_L40N_3/VREF_3
IO_L40P_3
IO/VREF_4
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4
IO_L27N_4/DIN/D0
IO_L27P_4/D1
IO_L30N_4/D2
IO_L30P_4/D3
IO_L31N_4/INIT_B
IO_L31P_4/DOUT/BUSY
IO_L32N_4/GCLK1
IO_L32P_4/GCLK0
IO/VREF_5
Pin Name
XC3S200
XC3S400
XC3S50
TQ144 Pin
Number
P124
P108
P107
P105
P104
P103
P102
P100
P99
P98
P97
P96
P95
P93
P92
P76
P74
P73
P78
P77
P80
P79
P83
P82
P85
P84
P87
P86
P90
P89
P70
P69
P68
P65
P63
P60
P59
P58
P57
P56
P55
P44
GCLK
GCLK
GCLK
VREF
VREF
VREF
VREF
VREF
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
VREF
Type
DCI
DCI
DCI
DCI
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
131