XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 17

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DCI answers these concerns by providing two kinds of
on-chip terminations: Parallel terminations make use of an
integrated resistor network. Series terminations result from
controlling the impedance of output drivers. DCI actively
adjusts both parallel and series terminations to accurately
match the characteristic impedance of the transmission line.
This adjustment process compensates for differences in I/O
impedance that can result from normal variation in the
ambient temperature, the supply voltage and the manufac-
turing process. When the output driver turns off, the series
termination, by definition, approaches a very high imped-
ance; in contrast, parallel termination resistors remain at the
targeted values.
DCI is available only for certain I/O standards, as listed in
Table
standard extensions to symbols or components. There are
five basic ways to configure terminations, as shown in
Table 9: DCI I/O Standards
DS099-2 (v2.5) December 4, 2009
Product Specification
Single-Ended
Gunning
Transceiver Logic
High-Speed
Transceiver Logic
Low-Voltage CMOS
Hybrid HSTL Input
and LVCMOS
Output
Category of Signal
9. DCI is selected by applying the appropriate I/O
Standard
R
GTL_DCI
GTLP_DCI
HSTL_I_DCI
HSTL_III_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
DIFF_HSTL_II_18_DCI
HSTL_III_DCI_18
LVDCI_15
LVDCI_18
LVDCI_25
LVDCI_33
LVDCI_DV2_15
LVDCI_DV2_18
LVDCI_DV2_25
LVDCI_DV2_33
HSLVDCI_15
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
Signal Standard
(IOSTANDARD)
(3)
Outputs
For
1.2
1.5
1.5
1.5
1.8
1.8
1.8
1.5
1.8
2.5
3.3
1.5
1.8
2.5
3.3
1.5
1.8
2.5
3.3
www.xilinx.com
V
CCO
(V)
Inputs
Table
terminations is put into effect.
HSTL_I_DCI-, HSTL_III_DCI-, and SSTL2_I_DCI-type out-
puts do not require the VRN and VRP reference resistors.
Likewise, LVDCI-type inputs do not require the VRN and
VRP reference resistors. In a bank without any DCI I/O or a
bank containing non-DCI I/O and purely HSTL_I_DCI- or
HSTL_III_DCI-type outputs, or SSTL2_I_DCI-type outputs
or LVDCI-type inputs, the associated VRN and VRP pins
can be used as general-purpose I/O pins.
The HSLVDCI (High-Speed LVDCI) standard is intended for
bidirectional use. The driver is identical to LVDCI, while the
input is identical to HSTL. By using a V
input, HSLVDCI allows greater input sensitivity at the
receiver than when using a single-ended LVCMOS-type
receiver.
For
1.2
1.5
1.5
1.5
1.8
1.8
1.8
1.5
1.8
2.5
3.3
1.5
1.8
2.5
3.3
1.5
1.8
2.5
3.3
10. The DCI I/O standard determines which of these
Spartan-3 FPGA Family: Functional Description
Inputs (V)
V
REF
0.75
0.75
1.25
1.65
0.8
1.0
0.9
0.9
0.9
1.1
0.9
-
-
-
-
-
-
-
-
for
Controlled driver with
impedance driver
impedance driver
half-impedance
At Output
Controlled
Controlled
Termination Type
Single
None
None
None
None
Split
REF
-referenced
At Input
Single
Single
Single
None
None
Split
Split
17