XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 55

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS099-3 (v2.5) December 4, 2009
DC Electrical Characteristics
In this section, specifications may be designated as
Advance, Preliminary, or Production. These terms are
defined as follows:
Advance: Initial estimates are based on simulation, early
characterization, and/or extrapolation from the characteris-
tics of other families. Values are subject to change.
Although speed grades with this designation are considered
relatively stable and conservative, some under-reporting
might still occur. Use as estimates, not for production.
Preliminary: Based on complete early silicon characteriza-
tion. Devices and speed grades with this designation are
intended to give a better indication of the expected perfor-
mance
under-reported delays is greatly reduced compared to
Advance data. Use as estimates, not for production.
Production: These specifications are approved only after
silicon has been characterized over numerous production
lots. There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes.
Parameter values are considered stable with no future
changes expected.
Production-quality systems must only use FPGA designs
compiled with a Production status speed file. FPGA designs
using a less mature speed file designation should only be
used during system prototyping or preproduction qualifica-
tion. FPGA designs with speed files designated as Advance
or Preliminary should not be used in a production-quality
system.
Whenever a speed file designation changes, as a device
matures toward Production status, rerun the
ISE
Table 27: Absolute Maximum Ratings
© 2003–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other coun-
tries. All other trademarks are the property of their respective owners.
DS099-3 (v2.5) December 4, 2009
Product Specification
Symbol
V
V
V
V
®
CCAUX
CCINT
V
CCO
REF
software
IN
of
Internal supply voltage relative to GND
Auxiliary supply voltage relative to GND
Output driver supply voltage relative to GND
Input reference voltage relative to GND
Voltage applied to all User I/O pins and
Dual-Purpose pins relative to GND
Voltage applied to all Dedicated pins
relative to GND
on the FPGA design to ensure that the FPGA
production
Description
(3)
silicon.
R
The
(2, 4)
probability
latest Xilinx
98
Driver in a
high-impedance
state
www.xilinx.com
of
0
Spartan-3 FPGA Family:
DC and Switching Characteristics
Product Specification
design incorporates the latest timing information and soft-
ware updates.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. The following
applies unless otherwise noted: The parameter values
published in this module apply to all Spartan
devices. AC and DC characteristics are specified using
the same numbers for both commercial and industrial
grades. All parameters representing voltages are mea-
sured with respect to GND.
Create a Xilinx MySupport user account and sign up for
automatic e-mail notification whenever this data sheet is
updated.
•
Mask and Fab Revisions
Some specifications list different values for one or more
mask or fab revisions, indicated by the device top marking
(see
involve the power ramp rates, differential DC specifications,
and DCM characteristics. The most recent revision (mask
rev E and GQ fab/geometry code) is errata-free with
improved specifications than earlier revisions.
Mask rev E with fab rev GQ has been shipping since 2005
(see
device shipments since 2006. SCD 0974 was provided to
ensure the receipt of the rev E silicon, but it is no longer
needed. Parts ordered under the SCD appended “0974” to
the
“XC3S50-4VQ100C” became “XC3S50-4VQ100C0974”.
Conditions
To Sign Up for Alerts on Xilinx MySupport
http://www.xilinx.com/support/answers/19380.htm
Package Marking, page
XCN05009
standard
Commercial
Industrial
All temp. ranges
) and has been 100% of Xilinx Spartan-3
part
–0.95
–0.85
–0.5
–0.5
–0.5
–0.5
–0.5
Min
number.
7). The revision differences
V
V
CCAUX
CCO
Max
1.32
3.00
3.75
4.4
4.3
For
+ 0.5
+ 0.5
example,
Units
V
V
V
V
V
V
®
55
-3