XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 130

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Spartan-3 FPGA Family: Pinout Descriptions
CP132 Footprint
130
44
14
7
0
Figure 43: CP132 Package Footprint (top view). Note pin 1 indicator in top-left corner and logo orientation.
I/O: Unrestricted, general-purpose user I/O
DCI: User I/O or reference resistor input for
bank
CONFIG: Dedicated configuration pins
N.C.: No unconnected pins in this package
A
B
C
D
G
H
K
M
N
E
F
L
P
J
VREF_7
L21N_7
L22N_7
L40N_6
L01P_6
L01P_7
VRN_7
L24P_7
L40N_7
L23P_6
L22N_6
VRN_6
GND
GND
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M0
M2
I/O
1
PROG_B
RDWR_B
L40P_7
L23N_6
L20P_6
L22P_7
L23N_7
VCCO_
L24P_6
VCCO_
L01P_5
L01N_5
L01N_7
VRP_7
CS_B
GND
LEFT
LEFT
I/O
I/O
I/O
I/O
I/O
M1
I/O
I/O
I/O
I/O
2
HSWAP_
BOTTOM
L21P_7
L40P_6
VREF_6
L24N_6
VREF_6
VCCO_
L22P_6
L20N_6
L01N_6
VCCO_
L27P_5
L01N_0
L24N_7
VRP_6
VRP_0
L23P_7
LEFT
GND
EN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3
VREF_5
VCCO_
L28N_5
L01P_0
L27N_5
VRN_0
L28P_5
TOP
GND
I/O
D7
D6
I/O
I/O
I/O
4
Bank 5
Bank 0
VCCAUX
VCCAUX
VCCINT
L31P_5
L27P_0
L27N_0
VCCO_BOTTOM for Bottom Edge Outputs
I/O
I/O
D5
I/O
5
12
12
8
4
VCCO_TOP for Top Edge Outputs
DUAL: Configuration pin, then possible
user I/O
GCLK: User I/O, input, or global buffer
input
JTAG: Dedicated JTAG port pins
GND: Ground
VCCINT
L30P_0
L30N_0
L31N_5
L32P_5
GCLK2
GND
D4
I/O
I/O
I/O
I/O
6
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BOTTOM
VREF_0
L31P_0
GCLK0
L32N_5
L32N_0
GCLK7
L31N_0
L32P_4
VCCO_
GCLK3
I/O
I/O
I/O
I/O
I/O
7
L32N_1
VCCO_
L31N_4
GCLK5
L32P_0
GCLK6
L31P_4
L32N_4
GCLK1
INIT_B
DOUT
BUSY
TOP
I/O
I/O
I/O
I/O
I/O
8
VREF_1
VCCINT
L31N_1
L30N_4
L30P_4
L32P_1
GCLK4
GND
D2
D3
I/O
I/O
I/O
I/O
9
VCCAUX
VCCAUX
VCCINT
L31P_1
L27N_4
L27P_4
10
DIN
D0
D1
I/O
I/O
I/O
Bank 1
Bank 4
11
12
4
4
BOTTOM
L28N_1
L28P_1
L27N_1
L01P_4
VCCO_
VRN_4
GND
11
I/O
I/O
I/O
VREF: User I/O or input voltage reference for
bank
VCCO: Output voltage supply for bank
VCCINT: Internal core voltage supply (+1.2V)
VCCAUX: Auxiliary voltage supply (+2.5V)
VREF_2
VREF_3
VREF_4
L20N_2
L24N_2
L24N_3
L20N_3
L27P_1
VCCO_
L01N_2
L21P_2
L40P_2
VCCO_
L01N_4
VRP_2
L23P_3
VRP_4
RIGHT
DS099-4 (v2.5) December 4, 2009
GND
TOP
12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF_2
L01P_1
L01N_1
VCCO_
L20P_2
VCCO_
L40P_3
L23N_3
L22P_3
L01N_3
VRP_1
VRN_1
RIGHT
L23N_2
L24P_2
RIGHT
VRP_3
DONE
GND
TDO
13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Product Specification
VREF_3
L21N_2
L40N_2
L23P_2
L40N_3
L24P_3
L22N_3
L20P_3
L01P_3
L01P_2
VRN_2
VRN_3
CCLK
TMS
GND
GND
TCK
14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DS099-4_17_011005
R